BICMOS cache TAG comparator having redundancy and separate read

Details BICMOS cache TAG comparator having redundancy and separate read BICMOS cache TAG comparator having redundancy and separate read

1994-06-21

1996-03-05

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Including signal comparison

365 49, 36518902, 365200, 36523002, G11C 1500

Patent

active

054973473

ABSTRACT:
A cache TAG comparator (20) has a combined data multiplexer and compare circuit (30) for multiplexing redundant columns (26) with normal columns of memory cells and for comparing input data with a TAG address stored in a TAG array (21) for determining if data required by a data processing system is located in a corresponding cache memory. A BICMOS match logic circuit (40) receives a compare signal from each data multiplexer and compare circuit, and provides a logic high match signal indicating a cache hit in response to a logic state of the input data and the TAG address being identical. The comparison is performed in ECL, allowing high speed operation. Also, the match signal is generated prior to a critical read path, insuring faster generation of the match signal.

REFERENCES:
patent: 4907189 (1990-03-01), Branson et al.
patent: 4996641 (1991-02-01), Talgam et al.
patent: 5031141 (1991-07-01), Guddat et al.
patent: 5067078 (1991-11-01), Talgam et al.
patent: 5184320 (1993-02-01), Dye
patent: 5280449 (1994-01-01), Oldham

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