BICMOS bit line load for a memory with improved reliability and

Details BICMOS bit line load for a memory with improved reliability and BICMOS bit line load for a memory with improved reliability and

1992-04-28

1993-03-23

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

365190, 365203, G11C 1140

Patent

active

051970325

ABSTRACT:
A BICMOS bit line load for a memory includes first and second bipolar transistors having emitters respectively coupled to first and second bit lines of a differential bit line pair. Collectors of the first and second bipolar transistors receive a reference voltage. An equalization signal is applied to bases of the first and second bipolar transistors. The equalization signal is at a logic low voltage during a write cycle, and at a logic high voltage otherwise. In order to decrease the worst-case reverse bias, which causes bipolar transistors to degrade over time, a difference between the logic high voltage and the logic low voltage of the equalization signal is limited to a predetermined voltage.

REFERENCES:
patent: 4953127 (1990-08-01), Nagahashi et al.

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