BiCMOS bit line load for a memory with improved reliability

Details BiCMOS bit line load for a memory with improved reliability BiCMOS bit line load for a memory with improved reliability

1990-07-06

1992-10-13

Dixon, Joseph L.

Static information storage and retrieval

Read/write circuit

For complementary information

365177, 36518909, 365203, 307544, 307570, G11C 1140

Patent

active

051557037

ABSTRACT:
A BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) bit line load for a memory with improved speed write recovery and improved reliability. Comprises a first bipolar transistor, a resistor, and a second and third bipolar transistors respectively coupled to first and second bit lines of a differential bit line pair. The improvement in speed is accomplished through the use of the bipolar transistors which generally switch faster than corresponding MOS transistors. The first bipolar transistor has a collector coupled to a power supply voltage terminal, a base for receiving a bias signal, and an emitter coupled to the collectors of the second and third bipolar transistors. The resistor is coupled between the collector and emitter of the first bipolar transistor. The bit line load has improved reliability by preventing self-boosting at the bases of the second and third bipolar transistors by decreasing their collector voltages enough during switching to bias them into saturation.

REFERENCES:
patent: 3949243 (1976-04-01), Sander et al.
patent: 4866674 (1989-09-01), Tran
patent: 4899317 (1990-02-01), Hoekstra et al.
Tran et al, An 8ns BiCMOS 1Mb ECL SRAM with a Configurable Memory Array Size, 1989 IEEE So State Circuits Conference, pp. 36-37.
Kertis et al, A 12nd 256K BiCMOS STEAM, 1989 IEEE Solid State Circuits Conference, pp. 186-187.
Burnett and Hu, Hot-Carrier Degradation in Bipolar Transistors at 300 and 110K-Effect on BiCMOS Inverter Performance, IEEE Transaction of Electron Devices, vol. 37, No. 4, Apr. 1990, pp. 1171-1111.

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