Static information storage and retrieval – Systems using particular element – Semiconductive
Reexamination Certificate
2001-06-29
2002-10-08
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Semiconductive
C365S174000, C365S163000, C365S148000, C365S203000, C365S225700, C365S051000
Reexamination Certificate
active
06462984
ABSTRACT:
BACKGROUND
This invention is generally related to techniques programming an array of memory cells (in a solid state integrated circuit device) that have a diode structure within each cell, and particularly related to a scheme for biasing the unselected wordlines and bitlines of the array, while applying a programming pulse to the selected wordline and bitline, to reduce reverse leakage of the diode structures in the array.
A diode structure can appear in a memory cell for a variety of reasons. For instance, in certain types of solid state memory devices that use a structural phase-change material as the programmable data storage mechanism, a parasitic diode is formed in series with the phase-change material. If the array is large and increased power consumption in the overall system is a concern, then the cumulative effect of reverse leakage in a large number of unselected cells becomes a problem whenever a small number of selected cells are being programmed. To help explain this problem, it is instructive to understand the circuitry in an exemplary memory cell and how a diode-based memory is programmed conventionally.
FIG. 1
shows a schematic circuit of part of an array
104
of diode-based phase-change material memory cells. The array
104
has a number of vertically oriented conductive lines
112
_
1
,
112
_
2
, . . .
112
_n−1,
112
_n,
112
_n+1, . . . (
112
), sometimes called bitlines, and a number of horizontally oriented conductive lines
108
_
1
,
108
_
2
, . . .
108
_n−1,
108
_n,
108
_n+1, . . . (
108
), sometimes called wordlines. The cross-point matrix arrangement of the bitlines
112
and the wordlines
108
allows each crossing of a bitline-wordline pair to be associated with a separate memory cell
114
having an index (i, j). To make it easier to explain the programming technique, only a 3×3 matrix of cells
114
, immediately surrounding the
114
_(n,n) cell, is shown in FIG.
1
. This description, however, is applicable to virtually any size of memory array.
To achieve low manufacturing costs in large volumes, every memory cell
114
in the array
104
may be designed to have the same structure. Thus, the cells are described using only one representative cell
114
_(n,n), where it is clear that the following description is applicable to all other cells in the array. The memory cell
114
_(n,n) has a diode structure
124
coupled between a separate bitline-wordline pair
112
_n−
108
_n that is selected when programming the cell
114
_(n,n). The diode structure
124
is oriented such that its forward current is in the bitline-to-wordline direction. In addition, the memory cell
114
_(n,n) has a volume of phase-change material
118
in series with the diode structure
124
and coupled between the bitline-wordline pair
112
_n-
108
_n. A fixed value matching resistor
120
is also in series with the diode structure
124
, coupled between the phase-change material
118
and the diode structure
124
. The material
118
acts as a programmable resistor and changes from one resistivity state to another, corresponding to a change from one type of structure to another, when the cell has been programmed.
Programming the memory cell
114
involves passing a current pulse through the phase-change material in that cell. This can be done by subjecting the bitline-wordline pair
112
_n−
108
_n of a target memory cell
114
_(n,n) to V
hi
and V
lo
, respectively. The difference V
hi
−V
lo
is sufficiently large so as induce the required programming current in the phase-change material. For instance, in a typical phase-change memory, a V
hi
−V
lo
of 2.5 Volts is sufficient to ‘reset’ the cell.
When one or more target memory cells are being programmed, the states of other cells in the array
104
should not be affected. In a conventional programming scheme applied to the array
104
shown in
FIG. 1
, this is achieved by first applying and maintaining V
hi
on all wordlines
108
and V
lo
on all bitlines
112
. This biasing scheme will strongly reverse-bias each diode structure
124
in every cell
114
of the array
104
, thereby causing a diode reverse leakage current through the phase-change material. Even at a relatively strong reverse-bias voltage of 2.5 Volts, the reverse leakage current is so small that the state of the phase-change material (and hence the cell) does not change.
While the diode structures in all cells are kept strongly reverse-biased as described in the previous paragraph, those bitline-wordline pairs that correspond to target memory cells are selected to be programmed. This is done by applying a pulse of V
lo
on the selected wordlines and V
hi
on the selected bitlines, while simultaneously keeping the unselected wordlines and bitlines at V
hi
and V
lo
, respectively. This condition of the array
104
which happens during the programming pulse is depicted
FIG. 1
where wordline
108
_n and bitline
112
_n are the selected bitline-wordline pair (corresponding to the target cell being cell
114
_(n,n)). Except for the target cell
114
_(n,n), it can be seen that the diodes in the other cells that are coupled to the selected bitline-wordline pair are zero voltage biased, and hence the state of these cells is not affected. All other cells of the array
104
that are coupled to the unselected wordlines and bitlines, however, remain strongly reverse-biased.
A problem with the conventional programming scheme described above is that biasing the unselected wordlines and bitlines at V
hi
and V
lo
, respectively, causes a relatively large, cumulative leakage current in a large array. For instance, consider a memory device having 1,000,000 cells arranged in a 1000×1000 array. Each time a cell in the device is programmed, the cells that are coupled to the 999 unselected wordlines and the 999 unselected bitlines are strongly reverse-biased at V
hi
−V
lo
. This means that the cumulative leakage current immediately before and during the programming of a single cell in such a device is on the order of 999×999 times the reverse leakage of one cell. This relatively high, cumulative leakage current in a memory device is not acceptable in many low power applications such as portable computing devices. Although a reduction in V
hi
−V
lo
will lower the leakage current, such a flexibility in the programming voltage may generally not be available due to the programming requirements of the cells. As an alternative, the diode structure in the cell may be specially designed to have extremely low leakage, even while strongly reverse biased. That solution, however, will increase the cost of manufacturing the device, due to special fabrication process steps or large cell area needed to form the diode structure separate from the rest of the circuitry in the device.
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