Biasing scheme for FIFO memories

Details Biasing scheme for FIFO memories Biasing scheme for FIFO memories

1989-07-17

1990-12-04

Bowler, Alyssa H.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365206, 365204, 365190, 3072961, G11C 1140, G11C 11702

Patent

active

049758799

ABSTRACT:
A biasing circuit for use with memory cells in intermittent memories includes means coupled between first and second bit-lines for biasing continuously the first and second bit-lines during a read operation so as to compensate for any leakage of charge without consumption any power. The biasing means is formed of an N-channel MOS biasing transistor (M1) and a cross-coupled half-latch circuit formed of a first P-channel MOS transistor (M2) and a second P-channel MOS transistor (M3).

REFERENCES:
patent: 4542485 (1985-09-01), Iwahashi et al.
patent: 4739499 (1988-04-01), Simpson
patent: 4740926 (1988-04-01), Takemae et al.
patent: 4817055 (1989-03-01), Arakawa et al.

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