Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold
Reexamination Certificate
1998-03-10
2001-02-06
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
C257S493000
Reexamination Certificate
active
06184565
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to semiconductor devices and is particularly directed to the biasing of support material surrounding a dielectrically isolated island, such as the fill material of a trench isolated integrated circuit architecture, so as to prevent the avalanche-generation of electron/hole pairs at a buried layer/island junction, which would otherwise limit the breakdown voltage of the device.
BACKGROUND OF THE INVENTION
Devices which contain a reverse-biased PN junction in the vicinity of adjoining regions of relatively high and low impurity concentrations are subject to the problem of an electric field-induced reduction in the breakdown voltage of that PN junction, where a conductor passes over a ‘high/low’ junction between adjoining regions of differential impurity concentration. In particular, an electric field may cause avalanche-generation of electron/hole pairs in the vicinity of the high/low junction. If the reverse-biased PN junction is within approximately a diffusion length of the location where the electron/hole pairs are generated, the charge carriers will be collected by the junction and appear as terminal currents, reducing the breakdown voltage of the PN junction.
An example of a device structure in which this problem occurs is described in an article by T. Mizoguchi et al, entitled “600V, 25A Dielectrically-Isolated Power IC with Vertical IGBT”, Proceedings of the Third International Symposium on Power Semiconductor Devices and ICs, 1991, pp 40-41. In such a device, the high-low junction is formed between a wrap-around N+ buried layer, which forms the outer side boundary of an island and the N− bulk of that island. The conductor which applies a high voltage to the high/low junction is the conductor which connects to the P diffusion that forms a PN junction with the island. The conductor must cross the high/low junction in order to connect the P region to one or more circuit elements in another island or in other islands. Techniques to reduce this problem include the formation of a region of intermediate doping to reduce the field a the high/low junction and increasing the insulator thickness between the conductor and the high/low junction.
I have discovered that this problem can also occur at the sidewall of a semiconductor-on-insulator structure having a bottom-located or buried layer (as opposed to a wrap-around layer). A bottom-located layer is often preferred over a wrap-around layer, since it allows the PN junction formed within the island to be placed closer to the sides of the island, as no space is consumed by the buried layer and it need not be spaced apart from a side layer. Consequently, eliminating the side layer allows manufacture of devices in smaller islands, thus reducing area and cost.
As an example,
FIG. 1
diagrammatically shows a dielectrically isolated semiconductor (e.g. N− type silicon) island
11
formed within a surrounding semiconductor (e.g. polysilicon) substrate
13
. Island
11
is dielectrically isolated from the substrate
13
by a layer of dielectric material (oxide)
15
, which extends from the top surface
17
of the structure along island sidewalls
21
, and also along the floor or bottom
23
of the island
11
. Island
11
contains a ‘buried’ high impurity concentration (N+) region
25
, which is contiguous with floor
23
and forms an N+/N− junction or interface
27
with the more lightly doped N-type material of the island
11
proper. Such a high impurity concentration buried layer may be employed as a subcollector region of a bipolar (NPN) transistor. The ‘high/low’ junction/interface
27
between N− type island
11
and highly doped (N+) buried layer
25
extends to the sidewalls
21
of the island, so that it abuts or intersects dielectric layer
15
. When a voltage is applied to and distributed throughout the substrate
13
, it gives rise to an electric field. Depending upon the ‘thinness’ of dielectric layer
15
and the magnitude of the substrate bias voltage, this electric field may be strong enough to induce the avalanche-generation of electron/hole pairs at interface
27
.
If the island architecture includes a reverse-biased PN junction in the vicinity of the island/buried layer interface
27
(for example, in the case of an NPN transistor, a reverse-biased collector-base junction
31
between N-island
11
and a P-base region
33
), and the reversed-biased PN junction (
31
in the example of
FIG. 1
) is within approximately a diffusion length of the location where the electron/hole pairs are generated, these charge carriers will be collected by the PN junction
31
and appear as terminal currents in the device. This substrate bias-induced terminal current limits the conduction or breakdown voltage of the collector-base junction of the device.
Without a side buried layer, one might attempt to solve the breakdown reduction problem by increasing the thickness of the surrounding oxide, one of the conventional methods mentioned above. Unfortunately, increasing the oxide thickness may require a very thick oxide (the Mizoguchi et al article, for example, describes an oxide thickness of 5.4 microns). A very thick oxide on the sides of an isolated island may cause stress which generated crystal defects in the islands which not only tend to produce devices with large current leakage, but also device which consume surface requiring extra area just does a side buried layer. The other prior art technique of forming an N graded region at the high/low junction might also be possible. However, the provision of such a region would require additional processing steps, increasing cost of manufacture. Even so, the above-reference article shows that a thick oxide may still be needed.
SUMMARY OF THE INVENTION
In accordance with the present invention, the unwanted reduction in breakdown voltage at the island sidewall with the dielectric is effectively countered by biasing the surrounding material, such as a support polysilicon substrate or the fill material of a surrounding dielectrically isolated trench, at a voltage that is not sufficiently different from the voltage of the island. By not sufficiently different is meant that the substrate bias voltage is insufficient to cause the avalanche-generation of electron-hole pairs in the vicinity of the relatively high-to-low impurity concentration junction between the buried layer and the island. Where a plurality of islands are supported in and surrounded by a common substrate material of an overall integrated circuit architecture, the prescribed bias voltage may be set at a value which differs from the island voltage by a value no more that half the total voltage applied to the integrated circuit. One mechanism for satisfying this requirement is to simply connect or (electrically) tie the substrate to the island bias voltage. This mechanism only applies to the case where the collectors of all sensitive devices are at the same voltage, since a continuous substrate allows only one substrate voltage in the integrated circuit. Thus, in the case of a vertical PNP transistor, for example, the substrate or trench may be connected to the most negative device voltage (the negative reverse bias voltage for the P-type collector island). conversely, in the case of a vertical NPN transistor, the substrate or trench voltage may be connected to the most positive device voltage (the positive reverse bias voltage for the N-type collector island).
In other words, the substrate or trench material is coupled to receive a prescribed bias voltage which has a value such that, when the substrate or trench is biased at that prescribed bias voltage, a nearby reverse-biased PN junction between a device region and the island has a breakdown voltage which is greater than its breakdown voltage when the substrate or trench is biased at the same bias voltage applied to the device region.
REFERENCES:
patent: 4361846 (1982-11-01), Tsukuda
patent: 5241210 (1993-08-01), Nakagawa et al.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Harris Corporation
Meier Stephen D.
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