Biasing an integrated circuit well with a transistor electrode

Details Biasing an integrated circuit well with a transistor electrode Biasing an integrated circuit well with a transistor electrode

1997-07-25

2000-10-17

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

252371, 438228, H01L 27108, H01L 2976, H01L 2994, H01L 31119

Patent

active

061335975

ABSTRACT:
Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMs and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage. This electrode overlaps the DNW which is biased to the same precharge voltage. This electrode provides the DNW N+ contact region.

REFERENCES:
patent: Re35613 (1997-09-01), Yasuda et al.
patent: 5281842 (1994-01-01), Yasuda et al.
patent: 5293055 (1994-03-01), Hara et al.
patent: 5297097 (1994-03-01), Etoh et al.
patent: 5348905 (1994-09-01), Kenney
patent: 5349218 (1994-09-01), Tadaki et al.
patent: 5373476 (1994-12-01), Jeon
patent: 5384474 (1995-01-01), Park et al.
patent: 5397734 (1995-03-01), Iguchi et al.
patent: 5404042 (1995-04-01), Okumura et al.
patent: 5521115 (1996-05-01), Park et al.
patent: 5595925 (1997-01-01), Chen et al.
patent: 5618740 (1997-04-01), Huang
patent: 5719733 (1998-02-01), Wei et al.
R. Rountree et al., "A Process-Tolerant Input Protection Circuit For Advanced CMOS Processes"; Electrical Overstress/Electrostatic Discharge Symposium Proceedings; Anaheim CA; Sep. 27-29, 1988, pp. 201-205.
R. Chapman, et al., "An 0.8 .mu.m CMOS Technology For High Performance Logic Applications", International Electron Devices Meeting Technical Digest, Washington, D.C., Dec. 6-9, 1987, pp.
G. Rieck, et al., "Novel ESD Protection For Advanced CMOS Output Drivers"; Electrical Overstress/Electrostatic Discharge Symposium Proceedings; New Orleans, LA; Sep. 26-28, 1989; pp. 182-189.
L.R. Avery, "Using SCR's As Transient Protection Structures In Integrated Circuits"; Electrical Overstress/Electrostatic Discharge Symposium Proceedings; Las Vegas, NV, Sep. 27-29, 1983, pp. 177-180.
R. Chapman, et al., "An 0.8 .mu.m CMOS Technology For High Performance Logic Applications", International Electron Devices Meeting Technical Digest, Washington, D.C., Dec. 6-9, 1987, pp. 362-365.
U.S. patent application Serial No. 08/760,121, filed Dec. 3, 1996, by L. Liu et al., entitled "Charging a Sense Amplifier".
Chatterjee et al., "A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads," IEEE Electron Devices, vol. 12, No. 1' pp. 21-22, Jan. 1991.

Affiliated with

Also associated with

Rating

Biasing an integrated circuit well with a transistor electrode does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Biasing an integrated circuit well with a transistor electrode, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Biasing an integrated circuit well with a transistor electrode will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-471702