Bias voltage applying circuit and semiconductor memory device

Details Bias voltage applying circuit and semiconductor memory device Bias voltage applying circuit and semiconductor memory device

2006-08-08

2006-08-08

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S185210, C365S185200

Reexamination Certificate

active

07088626

ABSTRACT:
Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.

REFERENCES:
patent: 6400606 (2002-06-01), Cho
patent: 6424571 (2002-07-01), Pekny
patent: 6563737 (2003-05-01), Khouri et al.
patent: 2003-077282 (2003-03-01), None
Castro, H.A. et al. (2002). “A 125MHz Burst Mode 0.18μm 128Mbit 2 Bits per Cell Flash Memory,”CLSI Symposium, 21.4:304-307.
Elmhurst, D. et al. (2003). “A 1.8V 128Mb 125 MHz Multi-level Cell Flash Memory with Flexible Read While Write” ISSCC Digest of Technical Papers 16.5:286-287.
European Search Report mailed Oct. 12, 2005 for European Patent No. 05250746.4, 3 pages.

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