Bias network for CMOS power devices

Details Bias network for CMOS power devices Bias network for CMOS power devices

1999-02-08

2001-01-16

Lee, Benny (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including push-pull amplifier

C330S268000

Reexamination Certificate

active

06175277

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to the field of complementary metal oxide semiconductor (“CMOS”) devices. More particularly, the present invention relates to an improved bias network for reducing cross-over distortion in Class A/B CMOS power audio amplifiers.
BACKGROUND OF THE INVENTION
Complementary metal oxide semiconductor (“CMOS”) devices are commonly used as transistors in a variety of integrated circuits. CMOS devices are especially popular due to their high-speed switching capabilities and extremely low power consumption. These devices are thus ideal for use as driver circuits, buffers, adders, memories and other electronic components requiring high speed and low power consumption. CMOS devices are widely used in computer systems and other consumer electronics including digital watches and calculators.
In addition, CMOS devices are also commonly used in audio equipment such as Class A/B audio amplifiers. Class A/B amplifiers combine the features of Class A amplifiers, which pass current at all time independent of the audio signal to be amplified, and Class B amplifiers, which use one transistor for amplifying the positive cycle of the audio signal and another for amplifying the negative cycle of the audio signal. The problem with Class A/B amplifiers in general is that high cross-over distortion often results at the “zero-volt line” when one transistor stops amplifying and the other begins.
To address the problem of high cross-over distortion, conventional CMOS audio amplifiers utilize specially designed electronic circuits to reduce cross-over distortion. A first conventional design utilizes an output stage having voltage to current translators, or “g
m
stages,” to bias the p-metal oxide semiconductor (“MOS”) and n-MOS devices into “OFF” states. However, because it is not possible to match the g
m
stages, a bias current flows through the p-MOS and n-MOS devices. As such, a greater cross-over distortion results through the zero-point thus providing a higher Total Harmonic Distortion (“THD”), which is severe at high frequencies where the gate of the p-MOS and n-MOS devices must quickly transition from zero volts (V
gs
=0) to a threshold voltage (V
gs
=V
t
), which is typically 0.7 to 1.0 volt. The first conventional circuit therefore utilizes low threshold p-MOS and n-MOS devices to ensure that the p-MOS and n-MOS devices never become depletion devices, i.e., the p-MOS and n-MOS devices are always operated in enhancement mode.
A second conventional circuit utilizes an additional g
m
stage that provides an extra bias gain that in effect “hides” the cross-over distortion of the CMOS device. Although this method provides good THD at low frequencies, the amount of loop gain is insufficient at high frequencies and thus the THD is again poor at high frequencies.
And lastly, a third conventional circuit utilizes a g
m
“helper” stage to provide an additional bias voltage for small voltage swings around the cross-over point. This solution has problems in that it requires quite a bit of silicon “real estate,” with the “helper” stage not having exactly the same gain and frequency response as the main output stage. Accordingly, as described above for the second conventional circuit, a g
m
stage must be added in front of the main output stage, i.e., the p-MOS and n-MOS g
m
stages, to linearize the gain near the cross-over point. The addition of this g
m
stage however again results on poor THD at high frequencies.
Therefore, a principle object of the present invention is to provide a bias network that reduces cross-over distortion in devices having complementary p-MOS and n-MOS power transistors.
Another object of the present invention is to provide a bias network that reduces cross-over distortion and provides improved total harmonic distortion in Class A/B audio amplifiers having complementary p-MOS and n-MOS power transistors.
Still another object of the present invention is to provide a bias network for a CMOS device that minimizes the number of electronic components required in an integrated circuit implementation of the CMOS device.
Further objects, features and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying figures showing illustrative embodiments of the invention.
SUMMARY OF THE INVENTION
The present invention relates to an improved bias network for minimizing cross-over distortion in a device having complementary p-MOS and n-MOS power transistors. In accordance with a preferred embodiment of the present invention, the improved bias network includes complementary helper transistors coupled to the power transistors for discharging currents while the power transistors are biased in sub-threshold regions of operation, complementary resistors coupled to the power transistors for biasing the power transistors within the sub-threshold regions and for biasing the helper transistors in saturation regions of operation, and complementary feedback circuits connected to the power transistors and operating in conjunction with the resistors for biasing the helper transistors within the saturation regions. Preferably, the improved bias network operates each of the power transistors just below their threshold voltages such that they may be biased into an on-state by a gate voltage swing of no more than 200 millivolts.
Advantageously, the improved bias network of the present invention is used to reduce cross-over distortion in Class A/B audio amplifiers having complementary p-MOS and n-MOS power transistors.


REFERENCES:
patent: 4015212 (1977-03-01), Miyata
patent: 4401954 (1983-08-01), Suzuki
patent: 5475343 (1995-12-01), Bee
patent: 5512859 (1996-04-01), Moraveji
patent: 5736902 (1998-04-01), Graeme

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