Bias level generating circuit in a flash memory device

Details Bias level generating circuit in a flash memory device Bias level generating circuit in a flash memory device

2000-11-27

2002-03-12

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S185230, C365S226000

Reexamination Certificate

active

06356488

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to a bias level generating circuit in a flash memory device for generating bias levels suitable for a programming or a programming verification of a cell.
BACKGROUND OF THE INVENTION
Referring now to
FIG. 1
, a bias level generating circuit in the conventional flash memory device will be explained below. The bias level generating circuit is consisted of a first inverter I
1
for inverting an enable signal EN, a first switching element P
1
for transferring the power supply to a charge pump
10
according to the output signal from the first inverter I
1
, a charge pump
10
, a voltage dividing diode, a regulation sense amplifier
20
, and switching elements and resistors for forming a current path.
The charge pump
10
generates a pump-out voltage PUMP_OUT according to the enable signal EN and the power supply. The voltage dividing diode is consisted of a plurality of diodes connected serially, for falling the pump-out voltage PUMP_OUT. The regulation sense amplifier
20
senses the signal the voltage of which is fallen by the plurality of diodes to generate a current path enable signal, according to the regulation enable signal REG_EN. The second switching element NI forms the current path to the output terminal of the charge pump
10
along with the first resistor R
1
, according to the output signal from the regulation sense amplifier
20
.
Below, the operation of the circuit will be explained.
If the enable signal EN is applied with a High state, the first inverter I
1
inverts the enable signal EN to turn on the first switching element P
1
. Then, the first switching element P
1
turned on transfers the power supply to the charge pump
10
. The voltage of the output signal from the charge pump has fallen by the plurality of diodes D
1
-D
4
and is applied to the regulation sense amplifier. Then, the regulation sense amplifier
20
driven according to the regulation enable signal REG_EN senses the output signal of the charge pump
10
the voltage of which has fallen, thus turning on the second switching element N
1
. Next, a current path extending from the pump-out voltage PUMP_OUT of the charge pump
10
to the first resistor R
1
is formed by the first switching element N
1
, so that the pump-out voltage is controlled to a bias level for use in a programming or a programming verification of the cell.
As mentioned above, in the conventional charge pump and regulation circuit structure, a single charge pump and a single regulator generate different biases levels necessary for a programming or a programming verification of a cell. Thus, the regulator having this structure has only a single current path (discharge path) and therefore the size of the transistor for current path must be fitted to a high bias. Therefore, in case that a low bias is generated using this circuit structure, there is a problem that it consumes a lot of time to discharge the current using a transistor for use in a high bias current path, in order to adjust the current to a desired level. Also, there is a problem that oscillation in the bias level is severe because a great current has to be discharged at a time. This oscillation causes malfunction in the programming verification of a flash memory cell.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a bias level generating circuit in a flash memory device capable of preventing oscillations, by which a bias level suitable for a corresponding operation is generated, when a programming operation or a programming verification operation is performed.
In order to accomplish the above object, a bias level generating circuit in a flash memory device according to the present invention is characterized in that it comprises a first inverter for inverting an enable signal, a first switching element switched depending on the output signal from the first inverter, a charge pump for generating a pump-out voltage necessary when generating a bias level depending on the power supply send via the first switching element and the enable signal, a bias switch circuit for preventing oscillation of the pump-out voltage in order to generate a bias level necessary for a programming or a programming verification of a cell, depending on a program signal, and a regulator for making the voltage generated in the bias switch circuit being a bias level suitable for the programming or the programming verification of the cell, by setting a specific path current depending on the program signal.


REFERENCES:
patent: 5291446 (1994-03-01), Van Buskirk et al.
patent: 5444412 (1995-08-01), Kowalski
patent: 5511026 (1996-04-01), Clevaland et al.
patent: 5822247 (1998-10-01), Tassan Caser et al.
patent: 6002630 (1999-12-01), Chuang et al.
patent: 6275099 (2001-08-01), Ghilardelli

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