Bias generator for low ground bounce output driver

Details Bias generator for low ground bounce output driver Bias generator for low ground bounce output driver

1994-05-20

1995-06-27

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 29, 326 31, H03K 1716, H03K 19003

Patent

active

054283035

ABSTRACT:
A bias generator circuit provides a bias control signal to the gate of a PMOS transistor which has been added to the inverter which drives the final NMOS pull-down transistor of a CMOS output driver circuit. The bias generator circuit includes a constant current source flowing from the positive supply. The bias generator circuit also includes a current difference circuit containing a resistive divider which drives the gate of an NMOS ballast transistor. This ballast transistor has process/voltage/temperature (PVT) characteristics corresponding to those of the final NMOS pull-down transistor in the CMOS output driver. The channel length of the NMOS ballast transistor and the final NMOS pull-down transistor are drawn the same. The ballast transistor subtracts a PVT adjusted current from the constant current source to produce a PVT adjusted output charging current. A down current mirror includes two PMOS transistors which are mirrored in the inverter which drives the final pull-down transistor of the CMOS output driver circuit. Thus, when this inverter is turned on, the charging current which flows at its output will mirror the PVT adjusted charging current flowing in the down current mirror. This produces a PVT adjusted voltage ramp on the gate of the final NMOS pull-down transistor. This PVT adjusted voltage ramp provides two important benefits: significantly reduced ground bounce and output driver falling delay which is independent of existing PVT conditions.

REFERENCES:
patent: 4584492 (1986-04-01), Sharp
patent: 4638187 (1987-01-01), Boler et al.
patent: 4645998 (1987-02-01), Shinohara et al.
patent: 4777389 (1988-10-01), Wu et al.
patent: 4782252 (1988-11-01), Levy et al.
patent: 4797579 (1989-01-01), Lewis
patent: 4820942 (1989-04-01), Chan
patent: 4894561 (1990-01-01), Nogami
patent: 4933574 (1990-06-01), Lien et al.
patent: 4959565 (1990-09-01), Knecht et al.
patent: 4961010 (1990-10-01), Davis
patent: 5008568 (1991-04-01), Leung et al.
patent: 5021684 (1991-06-01), Ahuja et al.
patent: 5028817 (1991-07-01), Patil
patent: 5028818 (1991-07-01), Go Ang et al.
patent: 5034637 (1991-07-01), Jungert
patent: 5036222 (1991-07-01), Davis
patent: 5036232 (1991-07-01), Jungert et al.
patent: 5049763 (1991-09-01), Rogers
patent: 5055714 (1991-10-01), Obregon
patent: 5059822 (1991-10-01), Dukes
patent: 5089721 (1992-02-01), Luich
patent: 5109166 (1992-04-01), Coburn et al.
patent: 5111076 (1992-05-01), Tarng
patent: 5121000 (1992-06-01), Naghshineh
patent: 5124579 (1992-06-01), Naghshineh
patent: 5148056 (1992-09-01), Glass et al.
patent: 5149991 (1992-09-01), Rogers
patent: 5153456 (1992-10-01), Keown
patent: 5168176 (1992-12-01), Wanlass
patent: 5173621 (1992-12-01), Fraser et al.
patent: 5173627 (1992-12-01), Lien
patent: 5206544 (1993-04-01), Chen et al.
patent: 5214320 (1993-05-01), Truong
patent: 5229666 (1993-07-01), Sandhu
patent: 5248907 (1993-09-01), Lin et al.
patent: 5268868 (1993-12-01), Kajigaya et al.

Affiliated with

Also associated with

Rating

Bias generator for low ground bounce output driver does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bias generator for low ground bounce output driver, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bias generator for low ground bounce output driver will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-289754