Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2002-01-10
2004-11-02
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S185210, C365S185180, C327S530000
Reexamination Certificate
active
06813194
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a bias distribution network, and more particularly to a bias distribution network for a memory.
Mixed mode non-volatile memory integrated circuit systems typically use bias across wide dimensions on a chip. Bias levels typically varies across the chip, because of physical boundary, power supply and temperature variation, or across multiple lots. However, a level bias across the chip is desired to ensure consistent performance for each memory cell, such as during programming or reading. For multilevel flash memory, the desire for a level bias is even more severe due to smaller margin per voltage level.
SUMMARY OF THE INVENTION
The present invention provides a memory device that has bias levels that are more consistent across the device.
The present invention also provides a testing method and apparatus to monitor and force the bias level.
The present invention provides a memory device that comprises an array of memory cells arranged in rows and columns. A portion of the array of memory cells is divided into segments. A global bias circuit generates a plurality of first bias currents. A plurality of local bias networks each comprise a local bias circuit that generates a plurality of second bias currents in response to a corresponding one of the plurality of first bias currents, and each comprises a plurality of segment bias circuits generating a third bias current. Each segment bias circuit is adjacent to a corresponding segment of said memory cells.
In one aspect, each segment bias circuit may provide a ground feedback signal to the local bias circuit, and in response thereto the local bias circuit adjusts the second bias current.
In one aspect, the segment bias circuits may be disposed in geometric positions in the segments.
In one aspect, the global bias circuit may include a global trim circuit to adjust the plurality of first bias currents in response to a global trim signal. Each local bias network may include a local trim circuit to adjust the plurality of second bias currents in response to a local trim signal.
REFERENCES:
patent: 6134141 (2000-10-01), Wong
patent: 6282145 (2001-08-01), Tran et al.
patent: 6396757 (2002-05-01), Quader et al.
patent: 6606265 (2003-08-01), Bergemont et al.
patent: 2002/0196664 (2002-12-01), Pascotti et al.
Saiki William John
Tran Hieu Van
Gray Cary Ware & Freidenrich LLP
Le Toan
Nguyen Van Thu
Silicon Storage Technology, Inc.
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