Bias current generating circuits and methods for integrated...

Details Bias current generating circuits and methods for integrated... Bias current generating circuits and methods for integrated...

1999-10-26

2001-03-13

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S512000

Reexamination Certificate

active

06201436

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit devices and operating methods, and more particularly to bias current generating circuits and methods for integrated circuits.
BACKGROUND OF THE INVENTION
Bias current generating circuits and methods are widely used in integrated circuits in order to generate a bias current for the integrated circuit, from an external power supply voltage. For example, field effect transistors such as Metal Oxide Semiconductor (MOS) transistors in an integrated circuit may be controlled by bias currents that are provided by a bias circuit.
In order to provide a controlled amount of bias current, it is desirable for the bias current to remain uniform, notwithstanding changes in the external power supply voltage, changes in temperature and/or integrated circuit fabrication process variations. Moreover, for high-speed integrated circuit devices such as high-speed integrated circuit memory devices, it is desirable for the bias current to rapidly reach a desired level when the integrated circuit transitions from a power-down state to a standby state or an active state. If excessive time is taken to generate the bias current, the operational speed of the integrated circuit may decrease and/or a malfunction may occur.
SUMMARY OF THE INVENTION
The present invention generates a bias current for an integrated circuit by generating a first bias current that increases with temperature of the integrated circuit, generating a second bias current that decreases with temperature, and summing the first bias current and the second bias current. Summing may take place by mirroring the first bias current, mirroring the second bias current and summing the mirrored first bias current and the mirrored second bias current. Pull-down circuits also are preferably provided for the circuits that generate the first and second bias currents. The pull-down circuits are responsive to a pulse signal. The pulse signal may be generated from a power-down signal or another signal. Accordingly, bias current generating circuits and methods can have reduced susceptibility to changes in temperature, changes in power supply voltage and/or process variations, and can rapidly produce the bias current.
More specifically, an embodiment of a bias current generating circuits according to the present invention comprises a first bias current generating circuit that includes a first output terminal and that generates a first bias current that increases with temperature. A second bias current generating circuit includes a second output terminal and generates a second bias current that decreases with temperature. A summing circuit is connected to the first output terminal and to the second output terminal, to sum the first bias current and the second bias current. A first pull-down circuit is connected to the first output terminal, to reduce the voltage of the first output terminal in response to a pulse signal. A second pull down circuit is connected to the second output terminal to reduce the voltage of the second output terminal in response to the pulse signal. A pulse generator is responsive to a transition of a signal, to generate the pulse signal. The summing circuit preferably comprises a first current mirror that mirrors the first bias current, a second current mirror that mirrors the second bias current and a summing node that sums the mirrored first bias current and the mirrored second bias current.
In a preferred embodiment, the first bias current generating circuit includes a first field effect transistor of a first conductivity type, a first field effect transistor of a second conductivity type, a resistor and a first diode that are serially connected between first and a second reference voltages. A second field effect transistor of the first conductivity type, a second field effect transistor of the second conductivity type and a second diode are serially connected between the first and the second reference voltages. The gates of the first and second field effect transistors of the first conductivity type are connected together to define the first output terminal. The gates of the first and second field effect transistors of the second conductivity type are connected together. The gate of the first field effect transistor of the first conductivity type is connected to the source or drain thereof and the gate of the second field effect transistor of the second conductivity type is connected to the source or drain thereof.
The second bias current generating circuit preferably comprises a first field effect transistor of a first conductivity type, a first field effect transistor of a second conductivity type and a resistor that are serially connected between a first and a second reference voltage. The gate of the first field effect transistor of the first conductivity type is connected to a source or drain thereof, to define the second output terminal.
The summing circuit preferably includes first and second field effect transistors that are connected between a reference voltage and a summing node. The first output terminal is connected to the gate of the first field effect transistor and the second output terminal is connected to the gate of the second field effect transistor.
The first pull-down circuit preferably includes a first field effect transistor that is connected between the first output terminal and a reference voltage, the gate of which is connected to the pulse signal. The second pull-down circuit preferably includes a second field effect transistor that is connected between the second output terminal and the reference voltage, the gate of which is connected to the pulse signal.
According to other embodiments of the present invention, a first current mirror is provided that is responsive to the summing circuit, to mirror the sum of the first bias current and the second bias current at an output terminal thereof. A second current mirror is responsive to the first current mirror, to mirror the current at the output terminal of the first current mirror. A third pull-down circuit is connected to the output terminal of the first current mirror, to reduce the voltage of the first output terminal in response to the pulse signal.
The first current mirror preferably includes first and second field effect transistors that are serially connected between the summing circuit and a reference voltage and third and fourth field effect transistors that are serially connected between the output terminal and the reference voltage. The gates of the first through fourth field effect transistors are connected to the summing circuit. The second current mirror preferably includes a fifth field effect transistor that is connected between a second reference voltage and the output terminal of the first current mirror, and a sixth field effect transistor that is connected to the second reference voltage. The gates of the fifth and sixth field effect transistors are connected to the output terminal of the first current mirror.
According to other embodiments of the present invention, the first bias generating circuit, the second bias generating circuit and the summing circuit may be provided, but the first and second pull-down circuits need not be provided. Accordingly, bias current generating circuits and methods according to the invention can have reduced susceptibility to temperature variations, power supply variations and/or microelectronic fabrication process variations and/or can rapidly provide a desired bias current.


REFERENCES:
patent: 4789819 (1988-12-01), Nelson
patent: 5349286 (1994-09-01), Marshall et al.
patent: 5798637 (1998-08-01), Kim et al.
patent: 6107868 (2000-08-01), Diniz et al.
patent: 6133718 (2000-10-01), Calafato et al.

Affiliated with

Also associated with

Rating

Bias current generating circuits and methods for integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bias current generating circuits and methods for integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bias current generating circuits and methods for integrated... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2489411