Bias circuits and methods for enhanced reliability of flash...

Details Bias circuits and methods for enhanced reliability of flash... Bias circuits and methods for enhanced reliability of flash...

2005-12-28

2008-10-07

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189090

Reexamination Certificate

active

07433235

ABSTRACT:
A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit.

REFERENCES:
patent: 5731720 (1998-03-01), Suzuki et al.
patent: 6809365 (2004-10-01), Nakamura et al.
patent: 6925009 (2005-08-01), Noguchi et al.
patent: 2005/0169021 (2005-08-01), Itoh
patent: 1996-042758 (1998-08-01), None
patent: 2002-133885 (2002-05-01), None
patent: 10-2002-0042749 (2002-06-01), None
patent: 10-2002-0094502 (2002-12-01), None

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