Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2000-10-11
2001-09-11
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S189090, C327S053000
Reexamination Certificate
active
06288960
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a bias circuit for read amplifier circuits for memories, and, more particularly, the memory is of the EEPROM type, which is capable of operating over a wide supply voltage range, such as 1.8-3.6 V, for example.
BACKGROUND OF THE INVENTION
When supply voltages on the order of 1.8 V are to be attained, the use of inverting amplifiers with an active load becomes necessary. These inverting amplifiers require a circuit capable of providing the appropriate bias voltage. Moreover, active load inverters have the advantage of allowing a high voltage and a temperature controlled biasing of the memory bit line if the dimensions of the transistor used as the inverter are appropriately chosen.
The bias circuit, however, requires a very large capacitor for coupling to the power supply for noise rejection. The circuit must therefore be able to drive large capacitive loads and must be allowed to reach a steady-state current value without current overshooting. This might cause malfunctions during the first reading of the memory after its power-on.
The circuit must also be able to power on in a very short time so that it is possible to switch off all the circuits related to the sense amplifier. This minimizes power consumption without penalizing the speed with which the first reading of the memory occurs.
Conventional circuits capable of providing a bias voltage are usually provided by current mirror structures which start from the reference current and achieve the intended bias current by a multiplication factor. A typical conventional structure is shown in
FIG. 1
, which is formed by a diode connected P-channel transistor P
1
and an N-channel transistor N
1
is connected in series. The transistors P
1
and N
1
are connected between a supply voltage Vdd and ground. A capacitor C is connected between the gate terminal of the transistor P
1
and the supply voltage Vdd.
If the circuit shown in
FIG. 1
must drive large capacitive loads C, it can be rendered very fast if the node VIPSENSE is precharged to the ground value at the beginning of each power-on. The main drawback of the circuit of
FIG. 1
is that this optimization is very difficult to provide for all kinds of processes, temperatures, models and supply voltages.
If the circuit is optimized for a supply voltage of 3 V, for example, while avoiding current overshooting, then the risk arises for making the circuit too slow at lower voltages, such as 1.8 V. The opposite is also true if the circuit is rendered fast enough for a supply voltage Vdd equal to 1.8 V, there is the risk of providing current overshooting for Vdd equal to 3 V. On the other hand, if the node VIPSENSE is made to start from a value which is close to the steady-state value, it is still necessary to place many buffers in parallel to each other to charge the capacitor C rapidly enough.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a bias circuit for read amplifier circuits for memories for setting a bias voltage very rapidly and without current overshooting.
Another object of the present invention is to provide a bias circuit for read amplifier circuits for memories that operate over a wide range of supply voltages, and independently of the processes and temperatures.
A further object of the present invention is to provide a bias circuit for read amplifier circuits for memories for charging the coupling capacitor with the supply voltage in a very short time.
Yet a further object of the present invention is to provide a bias circuit for read amplifier circuits for memories having good noise rejection.
Another object of the present invention is to provide a bias circuit for read amplifier circuits for memories that is highly reliable, relatively easy to provide and at competitive costs.
These objects and others which will become more apparent hereinafter are provided by a bias circuit for read amplifier circuits for memories, comprising at least one first circuit branch formed by a first pair of MOS transistors connected between a supply voltage and ground. The first pair of MOS transistors include a P-channel diode connected transistor and an N-channel transistor with an enable transistor interposed therebetween.
The first circuit branch drives a capacitive load for coupling to the supply voltage, characterized in that it comprises reference current amplifier circuit branches for amplifying a reference current which flows in the first circuit branch and is adapted to charge the capacitive load. The bias circuit further includes a circuit portion for controlling a charging current of the capacitive load. The control circuit portion comprises a feedback loop between the reference current amplifier circuit branches and the capacitive load.
REFERENCES:
patent: 5929658 (1999-07-01), Cheung et al.
patent: 6115316 (2000-09-01), Mori et al.
Conte Antonino
Gaibotti Maurizio
Zerilli Tommaso
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Hoang Huan
STMicroelectronics S.r.l.
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