Bias circuit for an FET

Details Bias circuit for an FET Bias circuit for an FET

1986-08-11

1988-06-07

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307304, 323354, H03K 301, G05B 2402

Patent

active

047498773

ABSTRACT:
A bias circuit for an FET comprises a voltage divider having two potential points. A first of the potential points is connected to a gate of the FET. The other potential point is connected through a second FET which may be turned off or on to vary the potential at the first potential point in order to control the bias on the gate of the first FET. The switching of the second FET is controlled as a function of a threshold voltage between its gate and a voltage in the source-drain circuit of the second FET. In one embodiment, a diode feedback circuit may be used to provide the threshold current.

REFERENCES:
"FET Ground Plus Bias Circuit", IBM Tech. Disc., vol. 27, No. 12, May 1985.

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