Bias cell for four transistor (4T) SRAM operation

Details Bias cell for four transistor (4T) SRAM operation Bias cell for four transistor (4T) SRAM operation

2001-12-31

2003-09-30

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S230060

Reexamination Certificate

active

06628540

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit memory circuits and operation methods.
Background: 4-Transistor Loadless SRAM
The four-transistor loadless SRAM cell (“4T-LL-SRAM”) is a recently-developed CMOS memory cell in which the states of the two data nodes are maintained in a distinctive way: not by a cross-coupled P-channel pair (as in the 6T cell), nor by resistive load elements (as in the old 4T NMOS cell), nor by refresh cycles (as in the 4T DRAM cells of the 1970s), but simply by leakage from the same pair of PMOS transistors which provide the pass gates for the cell. This cell, and various ways to use it, are described, for example, in copending U.S. provisional applications 60/259,276 filed Dec. 31, 2000 and 60/259,312 filed Dec. 31, 2000, both of which are hereby incorporated by reference.
For data retention, the high node must stay above a minimum voltage which is high enough to keep the opposite driver transistor reliably turned on. Thus the data retention requirement is that the P-channel pass transistor must source as much or more current to the high node, at this minimum voltage, as is sinked from the high node by leakage. The amount of current sourced by the pass transistors will be determined by the word line voltage: lower wordline voltages will cause the P-channel transistors in each cell to pass more current.
Despite the prospective advantages of the 4T-LL cell (e.g. less area than the 6T SRAM cell), it has not been extensively used. The primary reason is due to problems in optimizing the leakage current of the PMOS devices; if the leakage current of the P-channel devices is too low, data retention will be jeopardized; if leakage current is too high, excess power consumption will occur.
FIG. 4
shows the basic 4T-LL SRAM cell. The cross-coupled N-channel driver transistors
410
drive a pair of data nodes. A pair of P-channel pass transistors
420
, gated by a wordline WL\, connect these nodes to a pair of bitlines (not shown) when the wordline goes low. When access is not occurring, the P-channel pass transistors pass enough leakage current to keep one of the two nodes high. (Note that the pass transistors are not actually on: they simply pass a subthreshold leakage current which is enough to compensate for the modest subthreshold leakage current of the N-channel driver transistor which is pulling down the high node.)
Thus the leakage current of the PMOS devices must be maintained to a level higher than that of the NMOS. Until recently this was done by engineering the cell and process to minimize leakage for the NMOS and maximize leakage for the PMOS. This resulted in a cell with excessive leakage, particularly at high temperatures.
A more recent approach utilizes biasing the 4T cell PMOS devices to maintain a higher leakage than the NMOS devices. This results in reduced cell size, but the resulting cell is not a low current cell. (See e.g. K. Takeda et al., “A 16 Mb 400 MHz loadless CMOS Four-Transistor SRAM Macro”, ISSCC 2000, Paper TP16.1, which is hereby incorporated by reference.) In fact, the Takeda et al. paper specifically tries to keep the storage node very close to supply, increasing the leakage current to a very high level.
A particular quirk of the loadless 4T-SRAM cells is the importance of gate leakage components. The present inventors have realized that both gate leakage and subthreshold conduction are significant components of the balance of leakage currents. This makes optimization even more difficult.
Another quirk of the 4T-LL cell is that both high-temperature and low-temperature conditions are likely to be failure points for data retention.
Another difficulty in minimizing power consumption of the 4T-LL cell is that subthreshold conduction is sharply dependent on gate voltage, and thus the wordline voltage (under quiescent conditions) will very strong affect the power dissipation.
4T-LL SRAM Array with Quiescent Bias Referenced to Subthreshold Conduction of Parallelled Dummy Cells
The present application discloses an integrated circuit memory architecture in which a reference circuit monitors a reference array of SRAM cells, and adjusts the PMOS gate voltage of the data-containing cells to achieve a minimum storage voltage. This minimizes power consumption without jeopardizing data retention.
Advantages of the disclosed methods and structures, in various embodiments, can include one or more of the following:
Low power consumption;
Reduction of power consumption without increase in process complexity;
Joint optimization of power consumption, process complexity, speed, and bit error rate; and
Optimal (low) power consumption over the full range of permissible variation in temperature and supply voltage.
This is the first loadless-4T reference supply to include adjustment for gate leakage components. This will be particularly advantageous with the thin oxide 4T cell designs that will be developed in the next few months and years.
Another advantage is that implementation of 4T-LL-SRAM avoids the requirement for high-VT P-channel devices (as normally used in 6T SRAM cells), though in practice the availability of a high-VT-pmos can be convenient for reducing power consumption (with a 4T-LL-SRAM) to the absolute minimum.


REFERENCES:
patent: 5473568 (1995-12-01), Okamura
patent: 5793671 (1998-08-01), Selcuk
patent: 6087813 (2000-07-01), Tobita
patent: 6212124 (2001-04-01), Noda

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