Static information storage and retrieval – Read/write circuit – Including signal comparison
Patent
1989-07-07
1990-07-17
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Including signal comparison
36518909, 365174, 365177, 365203, 365154, 307279, G11C 700, G11C 800
Patent
active
049425552
ABSTRACT:
A semiconductor memory is provided having high reliability, and which particularly prevents data destruction by rays, and the like. In a semiconductor memory for detecting memory data from the conduction ratio between a transistor of a flip-flop type memory cell connected to selected word line and data line pairs and a load device of the data line, an arrangement is provided for setting the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of a data transfer MOS transistor of the memory cell. The signal read out from the memory cell is then applied through the data line to a differential amplifier using the base or gate of a junction type transistor as its input. Particularly to set the word line voltage to a voltage lower than the sum of the data line voltage and the threshold voltage of the data transfer MOS transistor of the memory cell, a device having high driving capability such as a bipolar transistor is used as the load of the data line. The word line voltage is changed over to two stages so that the data line voltage V.sub.D and the word line voltage V.sub.W satisfy the relation V.sub.W <V.sub.D +V.sub.TH in a read cycle and the relation V.sub.W >V.sub.D +V.sub.TH in a write cycle (where V.sub.TH is the threshold voltage of NMOS inside the memory cell).
REFERENCES:
patent: 4744063 (1988-05-01), Ohtani et al.
patent: 4747083 (1988-05-01), Nakajima et al.
Higuchi Hisayuki
Homma Noriyuki
Itoh Kiyoo
Suzuki Makoto
Garcia Alfonso
Hecker Stuart N.
Hitachi , Ltd.
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