Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2005-01-04
2005-01-04
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C257S907000
Reexamination Certificate
active
06839265
ABSTRACT:
There is provided a bi-level bit line architecture. Specifically, a DRAM memory cell and cell array are provided that allow for six square feature area (6F2) cell sizes and avoid the signal to noise problems. Uniquely, the digit lines are designed to lie on top of each other like a double-decker overpass road. Additionally, this design allows each digit line to be routed on both conductor layers, for equal lengths of the array, to provide balanced impedance. Now noise will appear as a common mode noise on both lines, and not as differential mode noise that would degrade the sensing operation. Furthermore, digit to digit coupling is nearly eliminated because of the twist design.
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Dinh Son T.
Micro)n Technology, Inc.
TraskBritt
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