Bi-layer programmable resistor memory

Static information storage and retrieval – Systems using particular element – Resistive

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Details

365100, 365104, 365177, G11C 1700, G11C 1714

Patent

active

059368802

ABSTRACT:
A static, in-circuit programmable memory device is provided where the storage element employed is a bi-layer programmable resistor. A specialized programming and readout circuit is provided for each storage element, allowing a known word-line/bit-line memory architecture (commonly used with fuse type memories) to be adapted to a memory element that conducts in both of two different states. The programming and readout circuit may take the form of a merged bipolar/FET device. A bipolar transistor is used for programming and also provides a diode action to prevent sneak path currents from flowing when a storage element is not selected. The bipolar transistor may be a parasitic bipolar transistor. An FET is used for readout. Storage elements are paired, one storage element of each pair functioning as a reference element. The bit lines of the paired storage elements are connected to a current mirror circuit that effects a comparison between current through the reference element and current through its paired storage element. Reliable readout is thereby attained.

REFERENCES:
patent: 4037218 (1977-07-01), Groeger
patent: 4070653 (1978-01-01), Rao
patent: 4583201 (1986-04-01), Bertin
patent: 5119329 (1992-06-01), Evans
patent: 5761110 (1998-06-01), Irrinki

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