Electrical pulse counters – pulse dividers – or shift registers: c – Shift register – Shift direction control
Reexamination Certificate
2003-06-05
2004-09-07
Wambach, Margaret (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Shift register
Shift direction control
C377S080000
Reexamination Certificate
active
06788757
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a shift-register circuit. In particular, the present invention relates to a bi-directional shift-register circuit for driving a liquid crystal display.
2. Description of the Related Art
A frame of a liquid crystal display (LCD) is generated by a plurality of pixels in a matrix. Thus, sequential pulses are basic signals driving the LCD. In addition, the sequential pulses are generated by a shift-register circuit, thus the shift register circuit is a general unit for the driving circuit of an LCD.
FIG. 1
shows a conventional shift-register circuit. Only three stages of shift-register units are shown in
FIG. 1 and a
plurality of shift-register units comprise a shift-register circuit. The input signals of the (N−1)th-stage shift-register unit
100
are the output signal (N−2)OUT of the (N−2)th-stage shift-register unit and the output signal (N)OUT of the (N)th-stage shift-register unit
102
. The input signals of the (N)th-stage shift-register unit
102
are the output signal (N−1)OUT of the (N−1)th-stage shift-register unit
100
and the output signal (N−1)OUT of the (N−1)th-stage shift-register unit
104
. The input signals of the (N−1)th-stage shift-register unit
104
are the output signal (N)OUT of the (N)th-stage shift-register unit
102
and the output signal (N−2)OUT of the (N+2)th-stage shift-register unit. In addition, the adjacent shift-register units receive inverted clock signals (CK or CK*). Accordingly, each shift-register unit operates in response to the output signal of the pre-stage shift-register unit and the next-stage shift-register unit and outputs data according to the voltage-level of the clock signal.
FIG. 2
shows a timing chart of the conventional shift-register unit. The output of the shift-register unit
100
is labeled (N−1)OUT, the output of the shift-register unit
102
is labeled (N)OUT and the output of the shift-register unit
104
is labeled (N+1)OUT. The data output from each shift-register unit is delayed by a half clock period. Thus, the requirement of the shift-register circuit is achieved.
However, a single sequence does not satisfy the requirement of LCD products. For example, some displays of digital cameras are rotated according to the placement angle of the camera. In addition, some LCD monitors provide a monitor rotation function so LCD displays with different scanning sequences are required. Therefore, a shift-register circuit with different signal output sequences is also required.
U.S. Pat. No. U.S. 5,894,296 (Maekawa 1999) discloses a bi-directional signal transmission network and bi-directional signal transfer shift register.
SUMMARY OF THE INVHNTZON
The object of the present invention is to provide another a bi-directional shift-register circuit comprising a plurality of shift-register units connected in serial. Each shift-register unit is connected to the pre-stage and the next stage shift-register unit. The direction of the data output sequence of the shift-register circuit is switched by controlling the switches and the control gate of the shift-register units.
To achieve the above-mentioned object, the present invention provides a bi-directional shift-register circuit comprising thin film transistors for outputting data in different turns according to a forward-scan control signal and a backward-scan control signal output by a scanning-sequence control circuit. The first shift-register unit with first-stage input terminal, a first-stage control terminal, and a first-stage output terminal outputs a first output signal. The second shift-register unit with second-stage input terminal coupled to the first-stage output terminal and a third-stage output terminal, a second-stage control terminal and a second-stage output terminal outputs a second output signal. The second-stage control terminal is selectively coupled to one first-stage output terminal and the third-stage output terminal and disables the second shift-register unit according to one first output signal and a third output signal. The third shift-register unit with third-stage input terminal, a third-stage control terminal, and a third-stage output terminal that outputs the third output signal. The switching circuit is coupled to the scanning-sequence control circuit for connecting the third-stage output terminal with the second-stage control terminal when receiving the forward-scan control signal, and connecting the first-stage output terminal with the second-stage control terminal when receiving the backward-scan control signal.
In addition, the present invention provides another bi-directional shift-register circuit having a plurality of shift-register units connected in serial for a clock signal, an inverse clock signal and a ground level. The or OR-logic gate receives signals output by output terminals of a pre-stage shift-register unit and a next-stage shift-register unit, respectively, and outputs an or-gate logic signal. The PMOS transistor includes a first gate, a first drain and a first source coupled to the or-gate logic signal. The first inverter is coupled between the first source and the first gate. The first NMOS transistor includes a second gate coupled to the first gate, a second drain coupled to the first drain and a second source. The switching circuit selectively outputs the signals of the output terminals of the pre-stage shift-register unit and the next-stage shift-register unit. The second inverter inverts the output signals. The AND-logic gate is coupled to the first drain and the second inverter for outputting an and-gate logic signal. The second NMOS transistor includes a third gate coupled to the AND-logic gate, a third drain coupled to the clock signal and a third source. The capacitor is coupled between the third gate and the third source. The third NMOS transistor includes a fourth gate coupled to the third gate, a fourth drain coupled to the inverse clock signal and a fourth source. The fourth NMOS transistor includes a fifth gate coupled to the first source, a fifth drain coupled to the third source and a fifth source coupled to the ground level. The fifth NMOS transistor includes a sixth gate coupled to the fourth source, a sixth drain coupled to the second source and a sixth source coupled to the ground level. The third inverter is coupled to the third source to output an inverted output signal. The fourth inverter is coupled to the third inverter to output the output signal.
REFERENCES:
patent: 4284953 (1981-08-01), Hepworth et al.
patent: 5282234 (1994-01-01), Murayama et al.
patent: 07-013513 (1995-01-01), None
Lu Shi-Hsiang
Yu Jian-Shen
AU Optronics Corp.
Ladas & Parry
Wambach Margaret
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