Bi-directional output buffer

Details Bi-directional output buffer Bi-directional output buffer

2001-12-21

2004-02-10

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S086000, C326S083000, C326S090000, C326S058000, C327S108000

Reexamination Certificate

active

06690191

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to digital communication systems, and more particularly to I/O devices.
2. Description of the Relevant Art
One issue that is typically considered when designing electrical communication systems is that of ringing, or reflections, on transmission lines. Various termination techniques are often utilized in order to reduce the ringing, and the resultant signal distortion, that may occur on a transmission line. For example, one or more electrically resistive elements (e.g., resistors) may be inserted between a driver and an end of a transmission line in order to cause the effective output impedance of the driver to more closely match the characteristic impedance of the transmission line. Similarly, one or more electrically resistive elements may be coupled to an end of a transmission line at a receiver in order to cause the effective input impedance of the receiver to more closely match the characteristic impedance of the transmission line.
FIG. 1A
illustrates one example of a driver and receiver which utilize termination. In the example shown, an output buffer (driver) includes transistors
180
and
182
configured to drive an output signal
124
. A receiver includes a comparator
190
coupled to receive an input voltage
186
and reference voltage Vref. A series resistor
186
has been added to the transmission line
183
in order to reduce signal reflections and distortion within the transmission line. Series resistor
186
may, for example, have a value equal to the characteristic impedance of the transmission line. A second termination resistor
184
, also having a value equal to the characteristic impedance of transmission line
183
, is connected between the first input terminal of op amp
190
and power supply voltage level VTT.
While both ends termination as illustrated in
FIG. 1A
reduces signal reflections, it also results in half amplitude received signals. When first termination resistor
186
and second termination resistor
184
are coupled to opposite ends of transmission line
183
in order to reduce signal reflections and distortion, they form a voltage divider network which restricts the range of voltage levels which may be used to convey signals from the driver to the receiver. Consequently, a more sensitive receiver is required.
FIG. 1B
illustrates one example of a typical bi-directional output buffer
100
. In the example shown, buffer
100
is coupled to memory modules
194
A-
194
B via bus
197
. Buffer
100
is configured to receive output enable
102
, data out
104
, and data in
106
. Included in buffer
100
are nand gate
130
, inverter
132
, and nor gate
134
. As is apparent from the figure, transistor
120
is turned on when both the output enable
102
and data out
104
are asserted, and the output signal
124
is driven via I/O pad
160
. If both the output enable
102
and data out
104
are low, then transistor
122
is turned on and a corresponding signal
124
driven out via I/O pad
160
. Bus
197
includes termination resistors
191
and
192
.
Buffer
100
is configured to both drive and receive signals. For example, buffer
100
may both write to, and receive data from, memory modules
194
. Generally speaking, output enable
102
will be negated when receiving data via I/O pad
160
. When output enable
102
is negated, both transistors
120
and
122
are turned off. Each of memory modules
194
include a particular output impedance. In general, the output impedance of buffer
100
may not be equal to that of memory modules
194
. Consequently, utilizing series resistor
191
to create an output impedance for buffer
100
which matches the characteristic impedance of bus
197
may be appropriate for when buffer
100
is driving, but may not be an appropriate value for when modules
194
are driving and buffer
100
is receiving.
What is desired is a bi-directional buffer with improved performance characteristics.
SUMMARY OF THE INVENTION
A bi-directional output buffer is contemplated which includes active termination. The buffer has at least two operating modes, including a driving mode and a receiving mode. A high impedance mode may also be included. When operating in driving mode, the buffer is configured to have an output impedance of a specified strength. When operating in a receiving mode, the buffer is configured to another specified impedance as an active termination. In addition to providing for differing driving and receiving impedances, the buffer may also be configured such that resistive components are shared between the driving and receiving modes.


REFERENCES:
patent: 5371424 (1994-12-01), Quigley et al.
patent: 5498990 (1996-03-01), Leung et al.
patent: 5532621 (1996-07-01), Kobayashi et al.
patent: 5652528 (1997-07-01), Kimura et al.
patent: 5929657 (1999-07-01), Choi
patent: 6054881 (2000-04-01), Stoenner
patent: 6127849 (2000-10-01), Walker
“SSTL for DIMM Applications”; Texas Instruments; Dec. 1997.
“EIA/JEDEC Standard”, Stub Series Terminated Logic for 3.3 Volts (SSTL_3), EIA/JESD8-8; Electronic Industries Association, Engineering Department; Aug. 1996.

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