Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2003-03-21
2004-10-19
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S095000, C326S121000, C327S208000
Reexamination Certificate
active
06806737
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to Very Large Scale Integrated (VLSI) circuit accelerated bus line communication. In particular, the present invention relates to bus amplification circuits.
BACKGROUND OF THE INVENTION
Highly integrated circuits such as microprocessors, application specific integrated circuits (ASICs) and some memory devices utilize bus lines for the communication of data between at least two points. In memory devices for example, data buses are used to carry data from the memory core to input/output pads. In microprocessors and ASICs, buses are commonly used to carry information to various blocks within the chip. Data buses can be uni-directional, where data is always transmitted in one direction, or bi-directional, where data can be transmitted in either direction. In both types however, the speed at which data is transmitted along the data bus can limit the overall performance of the integrated circuit.
Another type of integrated circuit device that makes use of bus lines is computational random access memory (CRAM). CRAM is a memory device having arrayed parallel processors with hundreds to thousands of processors commonly connected to a shared bus line. CRAM is a processor in memory architecture that takes advantage of the large internal memory bandwidth available at the sense amplifiers. By pitch matching each bit serial processing element (PE) to one or more memory columns, CRAM can operate as a massively parallel single instruction stream, multiple data stream (SIMD) computer. CRAM architectures and arrayed parallel processor architectures are well known in the art.
An example of a prior art CRAM is shown in FIG.
1
. The CRAM
20
shown in
FIG. 1
includes two banks
22
and
24
, labeled “Bank 1” and “Bank 2” respectively, although a CRAM can contain any number of banks. Bank
22
includes a memory array
26
coupled to peripheral circuits such as row decoders
28
, processing elements (PEs)
30
, and column decoders
32
. Bank
24
is identically configured to bank
22
, and includes a memory array
34
coupled to peripheral circuits such as row decoders
36
, PEs
38
, and column decoders
40
. Memory arrays
26
and
34
can be of any type of memory, such as dynamic random access memory (DRAM) or static random access memory (SRAM), for example, with row decoders
28
and column decoders
32
selecting particular memory cells for read and write operations. Each PE
30
has direct access to a single column of memory for use as its local memory, and is coupled to a common broadcast bus
42
. As shown in
FIG. 1
, PEs
30
and
38
are all coupled to the same broadcast bus
42
, which can further extend to other banks of the chip. The PEs
30
are connected to the common broadcast bus
42
in a wired AND configuration, allowing the common broadcast bus
42
to function as a dynamic zero detect circuit. Furthermore, if at least one PE
30
writes a zero to the common broadcast bus
42
, all other PEs
30
receive the zero value for register write back.
An example of a prior art PE
30
or
38
used in CRAM
20
of
FIG. 1
is shown in
FIG. 2. A
pair of adjacent PEs
30
are shown in
FIG. 2
, illustrating the interconnections between each other and the broadcast bus
42
. The presently shown PEs
30
support bit-serial computation, left-right nearest-neighbor communication, wired-AND broadcast bus evaluation and external databus access. The data processing components of PEs
30
are not relevant to the present invention and hence not discussed in detail, except for transceivers
50
which are responsible for communicating data between the PE
30
and the broadcast bus
42
. The memory can also be accessed externally through a conventional databus
52
connected to sense amplifier circuit
54
.
Because the broadcast bus
42
is long, and is capacitively loaded due to the numerous transceivers
50
connected to it, global communication between PEs
30
via the wired AND broadcast bus line is slow. As is known to those of skill in the art, factors that limit bus speed performance are its capacitive load and wiring resistance, both of which increase in proportion to its wiring density and length. The capacitive load of the bus also increases as more transistors, such as transceivers
50
, are coupled to it.
Hence, the switching rate and the time to reverse bus line charge are degraded and overall performance is adversely affected. Unfortunately, maximum device performance demands that charge reversal of the bus line be completed within the shortest time possible while taking into account adequate noise margins while ensuring reliable data recognition.
The circuits and techniques proposed in the art for improving bus line performance include mid-point precharge schemes, sensing of small voltage changes, segmenting bus lines, and other various schemes for reducing bus line capacitance or speeding up signal transmission. Unfortunately, many of the proposed solutions are not suitable for bi-directional signal transmission since their circuits require control signals to indicate the direction of the data. This can add design overhead and impose control signal timing constraints.
It is, therefore, desirable to provide a bus amplifier circuit and method for providing high-speed operation of a bi-directional bus line.
SUMMARY OF THE INVENTION
It is an object of the present invention to obviate or mitigate at least one disadvantage of previous bi-directional bus line amplifier circuits and methods. In particular, it is an object of the invention to provide a high-speed bi-directional bus line architecture.
In a first aspect, the present invention provides a bi-directional amplifier circuit for driving data between first and second complementary bus lines and third and fourth complementary bus lines. The bi-directional amplifier circuit includes a precharge circuit, a pre-discharge circuit, discharge circuit, and a charge circuit. The precharge circuit charges the first bus line to a high logic level. The pre-discharge circuit discharges the second bus line to a low logic level. The discharge circuit drives the first bus line to the low logic level in response to a change in the logic level of one of the second bus line and the fourth bus line. The charge circuit drives the second bus line to the high logic level in response to a change in the logic level of one of the first bus line and the third bus line.
In an embodiment of the present aspect, an enable signal activates the discharge circuit and disables the pre-discharge circuit, and an inverted enable signal activates the charge circuit and disables the discharge circuit. The precharge circuit includes a p-channel transistor having a gate terminal for receiving the enable signal, and the pre-discharge circuit includes an n-channel transistor having a gate terminal for receiving the inverted enable signal.
According to an aspect of the present embodiment, the discharge circuit includes a first discharge transistor for discharging the first bus line to the low logic level in response to the high logic level of the fourth bus line, and the charge circuit includes a first charge transistor for charging the second bus line to the high logic level in response to the low logic level of the third bus line. In the present aspect, the discharge circuit includes second and third discharge transistors serially connected between the first bus line and VSS, where the second discharge transistor has a gate terminal for receiving the second bus line, and the third discharge transistor has a gate terminal for receiving the enable signal. The charge circuit includes second and third charge transistors serially connected between the second bus line and VDD, where the second charge transistor has a gate terminal for receiving an inverted enable signal, and the third charge transistor has a gate terminal for receiving the first bus line.
In an alternate embodiment of the present aspect, the discharge circuit includes a second discharge transistor connected between the first bus line and the enable signal, an
Brandon Tyler Lee
Elliot Duncan George
Koob John Conrad
Sung Raymond Jit-Hung
Hamilton Brook Smith & Reynolds P.C.
Tan Vibol
LandOfFree
Bi-directional amplifier and method for accelerated bus line... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bi-directional amplifier and method for accelerated bus line..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bi-directional amplifier and method for accelerated bus line... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3259869