Bi-CMOS output buffer circuit for CMOS-to-ECL conversion

Details Bi-CMOS output buffer circuit for CMOS-to-ECL conversion Bi-CMOS output buffer circuit for CMOS-to-ECL conversion

1995-02-22

1996-10-01

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326126, 326 84, H03K 190948, H03K 190175, H03K 19082

Patent

active

055613829

ABSTRACT:
The logic of an intermediate signal (Y.sub.1) goes high when an input signal (CI) makes an "L" to "H" transition, and then a transistor (Q.sub.1) turns on and a transistor (Q.sub.2) turns off. The input signal (CI) at a potential corresponding to the logic "H" at a CMOS level has been applied to the gate of an NMOS transisitor (N.sub.1), and the NMOS transistor (N.sub.1) turns on rapidly. At this time, only current flowing through the base of an output transistor (Q.sub.0) flows through parallel connection of a resistor (R.sub.2) and an on-resistance of the NMOS transistor (N.sub.1). Since the NMOS transistor (N.sub.1) is on, the base potential of the output transistor (Q.sub.0) is raised if the resistor (R.sub.2) has a high resistance, and current fed from the output transistor (Q.sub.0) increases, thereby raising the emitter potential of the output transistor (Q.sub.0). Then the logic of an output signal (EO) goes high. Power consumption of an output buffer circuit is reduced.

REFERENCES:
patent: 5029479 (1991-06-01), Jeffery et al.
patent: 5237214 (1993-08-01), Usami
patent: 5331229 (1994-07-01), Barre
MECL System Design Handbook, May 1980, pp. 4 and 5.
JP 59-67728, Apr. 17, 1984, 2 pages.
JP 63-313916, Dec. 22, 1988.

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