Bi-CMOS merged devices

Details Bi-CMOS merged devices Bi-CMOS merged devices

1995-04-28

1998-09-22

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257378, 257413, 257588, 257754, 257755, H01L 2976, H01L 2994, H01L 27082, H01L 2348

Patent

active

058118608

ABSTRACT:
A merged BiCMOS device 10 having a bipolar transistor 60 and a PMOS transistor 64 formed in the same well region 18. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. Emitter electrode 30 is separated from base region 26 by thick oxide 24. Tungsten-silicide layer 32 covers emitter electrode 30. PMOS transistor 64 comprises source/drain regions 52 and 52a, gate electrode 40, and gate oxide 36. PMOS transistor 64 may optionally comprise LDD regions 44. Source/drain region 52a is in contact with base region 26. If desired, the emitter electrode 30 and gate electrode 40 may be silicided.

REFERENCES:
patent: 4868135 (1989-09-01), Ogura et al.
patent: 5031020 (1991-07-01), Momose
patent: 5101257 (1992-03-01), Hayden et al.
patent: 5334549 (1994-08-01), Eklund
Rovedo et al., Process Design for Merged Complementary BiCMOS, IEEE 1990, pp. 485-488.

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