Bi-CMOS logic circuit

Details Bi-CMOS logic circuit Bi-CMOS logic circuit

1987-03-30

1988-04-26

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307570, 307279, H03K 1901, H03K 19003, H03K 19082, H03K 19094

Patent

active

047407182

ABSTRACT:
A Bi-CMOS logic circuit having a totem pole-type output buffer, a CMOS logic circuit, and a latch circuit. The output buffer comprises a pull-up NPN bipolar transistor and a pull-down NPN bipolar transistor. The CMOS logic circuit controls the base current of the pull-up NPN bipolar transistor. The latch circuit controls the base current of the pull-down NPN bipolar transistor. The latch circuit includes at least two N-type MOSFETs. The first MOSFET has a gate coupled to the input terminal of the CMOS logic circuit, a drain connected to the node of the first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor. The second MOSFET has a drain coupled to the input terminal of the CMOS logic circuit, a gate connected to the node of the first and second NPN bipolar transistors, and a source coupled to the base of said second NPN bipolar transistor.

REFERENCES:
patent: 4616146 (1986-10-01), Lee et al.
patent: 4649295 (1987-03-01), McLaughlin et al.
patent: 4661723 (1987-04-01), Masuda et al.
patent: 4694203 (1987-09-01), Uragami et al.
Japanese Patent Disclosure (KOKAI) No. 59-25423, Feb. 9,1984.

Affiliated with

Also associated with

Rating

Bi-CMOS logic circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bi-CMOS logic circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bi-CMOS logic circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-821810