Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1998-06-04
2002-09-10
Eckert, II, George C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S737000, C257S780000
Reexamination Certificate
active
06448647
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a BGA (Ball Grid Array) package substrate for mounting a semiconductor device such as LSI.
2. Prior Art
In recent years, BGA packages have attracted attention as surface mounting packages for mounting semiconductor devices.
FIG. 4
a schematically shows the structure of a conventional BGA package.
As shown in
FIG. 4
a
, a BGA package
101
is designed to mount a semiconductor device
103
such as an LSI chip on one surface of a printed wiring board
102
and to form solder balls
104
as outer electrodes on the back surface.
In this BGA package
101
, bonding wires
105
connected to electrode pads
103
a
on the semiconductor device
103
are connected to a conductive pattern
106
formed on the printed wiring board
102
. This conductive pattern
106
is connected to lands
108
a
of a conductive pattern
108
formed on the back surface of the printed wiring board
102
through via holes
107
passing through the printed wiring board
102
, whereby the electrode pads
103
a
of the semiconductor device
103
are connected to the solder balls
104
.
The BGA package
101
with such a structure can be used as CSP (Chip Size/Scale Package) with a small packaging area to permit high-density surface mounting of various types of semiconductor devices
103
.
However, this type of conventional BGA package
101
had the problem that a solder resist layer
109
made of a resin such as polyimide on the back surface of the printed wiring board
102
as shown in
FIG. 4
b
expands or contract during temperature cycling tests, for example, to cause a stress in the solder balls
104
, which invites microcracks lowering the reliability of connection to a mother board, because the solder resist layer
109
is designed to come into contact with the solder balls
104
in the conventional BGA package
101
.
In order to solve this problem, a BGA package was proposed wherein the diameter of the lands
108
a
of the conductive pattern
108
formed on the back surface of the printed wiring board
102
is reduced and the solder resist layer
109
is kept out of contact with the lands
108
a
, as shown in
FIG. 4
c
, for example.
However, the conventional example shown in
FIG. 4
c
had the problem that an opening
110
formed in the solder resist layer
109
to receive solder balls
104
should have a diameter comparable to the diameter of the solder ball
104
, which hinders fine-pitch packaging.
Another problem of this conventional example is that the printed wiring board
102
must have great rigidity and thickness to reliably retain the lands
108
a
because the solder resist layer
109
is not designed to overlap the periphery of each land
108
a
for receiving a solder ball
104
, whereby it was difficult to construct with a thin substrate made of a resin such as polyimide.
If such a structure as shown in
FIG. 4
c
is applied to a thin substrate with low rigidity made of a resin such as polyimide, the pattern of the land
108
a
may be peeled or a plating layer on the surface of the land
108
a
may be peeled. As a result, it was difficult to obtain a thin and light BGA package with such a structure.
The present invention was made to solve these problems of the prior art, particularly with the object of providing a BGA package substrate capable of forming a thin and light BGA package which causes no crack in solder balls during temperature cycling tests and which permits fine-pitch packaging.
SUMMARY OF THE INVENTION
In order to attain the above object, the invention of claim
1
provides a BGA package substrate comprising an electrode for connection to an IC and an electrode for connection to a mother board on a circuit board consisting of a conductive circuit formed on an insulating base wherein at least said electrode for connection to a mother board is in the form of a solder ball, characterized in that an opening is formed in said insulating base in such a manner that the periphery of a connecting land to be formed the solder ball-like electrode thereon of said conductive circuit may be overlapped by said insulating base and that an end of said opening in said insulating base is tapered.
According to the invention, the tapered end of the opening in the insulating base allows the area of the end of the opening to be greater than the area of the connecting land exposed at the bottom, with the result that the solder ball-like electrode can be kept out of contact with the end of the opening of the insulating base even if the opening is formed in the insulating base to leave an overlap on the periphery of the connecting land.
Accordingly, the invention prevents any microcrack due to stress during temperature cycling tests in the solder ball-like electrode.
There is no possibility that the conductive pattern on the connecting land portion might be peeled or the plating layer on the surface of said land might be peeled even if a thin resin is used as an insulating base, because the connecting land is retained by the insulating base.
In this case, the invention is effective when the angle of the taper is 70° or less with the connecting land of the conductive circuit.
According to the invention, contacts between the end of the opening of the insulating base and the solder ball-like electrode can be more reliably prevented.
REFERENCES:
patent: 4807021 (1989-02-01), Okumura
patent: 5607099 (1997-03-01), Yeh et al.
patent: 5668386 (1997-09-01), Makiuchi et al.
patent: 5777382 (1998-07-01), Abbott et al.
patent: 5841192 (1998-11-01), Exposito
patent: 5844168 (1998-12-01), Schueller et al.
patent: 5844316 (1998-12-01), Mallik et al.
patent: 5851911 (1998-12-01), Farnworth
patent: 6046598 (2000-08-01), Miyaji et al.
patent: 9-260540 (1997-10-01), None
Notification for Reasons for Refusal from Japanese Patent Office, dated Feb. 20, 2001, 3 pages.
Fujimoto Masahiro
Kurita Hideyuki
Eckert II George C.
Rosenthal & Osha L.L.P.
Sony Chemicals Corporation
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