Behavioral silicon construct architecture and mapping

Details Behavioral silicon construct architecture and mapping Behavioral silicon construct architecture and mapping

1999-05-07

2001-10-02

Niebling, John F. (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06298472

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to logic synthesis of a logic circuit or ASIC.
2. State of the Art
Logic synthesis tools are used to interpret a description of a hardware circuit or logic ASIC so as to generate a final optimized silicon implementation of the circuit or system. Currently, most logic hardware (e.g., in ASIC form) is modeled and simulated by a designer writing an RTL (register-transfer level) description which corresponds to the function to be performed by the hardware or system. A RTL description is a hardware description language (HDL) description which describes the ASIC in terms of structural elements such as AND, NAND, or NOR gates. These gates are either explicitly called out or implicitly inferred by a boolean equation. The RTL description may also specify sequential elements such as latches and flip flops. There may also be a finite state machine description specifying a state transition graph. The following is an example of an RTL description:
EXAMPLE 1
module synAssign (f, a, b, c);
output f;
input a, b, c;
assign f = (a & b & c) | (a & −b & −c) | (−a & (b|c));
endmodule
The RTL language description is then used as input into a RTL synthesis tool which first reads and manipulates the RTL description in order to simplify the combinational logic, maps the manipulated description to a library of available standard cells, and then generates a description of the circuit in terms of actual physical gates and wire connections usable by a CAD tool to design the final gate level structure of the system. Essentially, a logic synthesis tool reads the logic functionality specified by the RTL description and tries to optimize the final gate design with respect to design constraints and library elements.
FIG. 1
shows an example of a synthesized hardware design implementation of the RTL description shown in EXAMPLE 1 using specified standard cells within the library of the synthesis tools. Other hardware design implementations are possible with alternate libraries and performance constraints.
FIG. 2
summarizes the steps performed to obtain a hardware description using RTL synthesis which basically includes writing a RTL description which corresponds to the functional behavior of an ASIC or logic system and providing the RTL description to a RTL synthesis tool which, in turn, generates a corresponding gate and interconnect description.
Part of the problem with using RTL descriptions and synthesis to simulate logic hardware is that it is easier for designers to view and understand a complex logic ASIC at more of an abstract or functional level than at a RTL gate level. For instance, a designer might want to design a piece of hardware which performs some transform function on an input signal and generates an output signal in a specified number of cycles and having a specified number of pipelines. Ideally, a designer would like to describe the function of the ASIC or a programming kernal of computation in terms of a programming language (e.g., C programming language), provide this to a synthesis tool, and generate a hardware description of the ASIC which can be easily manipulated to view different implementations of the ASIC optimized for different design considerations. The prior art method does not provide this capability. Another significant disadvantage of the prior art method is that the task of describing an algorithm or circuit function in terms of a RTL description can take many man-years of effort for complex algorithms as in a system that performs a quadrature amplitude modulation (QAM) using functional building block functions such as a FFTs (Fast Fourier Transforms).
Recently, in order to close the gap between the RTL type level description and the abstract level description design technique as desired by system designers, a behavioral synthesis technique has been developed which allows the designer to describe the ASIC in terms of abstract constructs via a behavioral language. Hence, whereas traditional RTL descriptions correspond to individual system level hardware components (e.g. AND, OR gates), a behavioral description in no way implies a specific piece of hardware. For instance, writing a “+” operator in an RTL description creates an instance of a specific adder or declaring a variable A creates a register. However, when an addition operation is specified in a behavioral description, this in no way implies what particular type of adder will be part of the hardware implementation. In fact, a behavioral description can closely resemble a programming language. The following is an example of a Verilog behavioral description:
EXAMPLE 2
@(posedge Clock)   //St1
A;
while (flag1) begin
B;
if (flag2) begin
C;
@(posedge Clock)   //St2
D;
end
else begin
E;
@(posedge Clock)   //St3
F;
end
end
G;
@(posedge Clock)   //St4
H;
As can be seen in EXAMPLE 2, gates are not explicitly called out and instead the description is in terms of clock edges (e.g., @(posedge Clock)), states St
1
-St
4
, and process loops A-H.
The behavioral language is provided to a behavioral synthesis tool which then generates a RTL language description. This process is referred to as behavioral synthesis. The RTL description specifies the functional elements for implementing the logic design depending on the functional units and operators that are available to the behavioral tool (e.g., ALUs, memories, registers, muxes, and controllers). In general each behavioral tool includes a library of functional units and operators which it uses to generate a RTL description. The RTL description is then provided to a RTL synthesis tool which in turn generates a hardware description of the ASIC in terms of standard gates and their interconnections according to the RTL synthesis tool's specified cell library.
FIG. 3
summarizes the steps performed to obtain a hardware description using behavioral synthesis which basically includes writing a behavioral description corresponding to the function of an ASIC or logic hardware, providing the behavioral description to the behavioral synthesis tool so as to generate a RTL description of the ASIC or logic hardware, providing the RTL description to a RTL synthesis tool which, in turn, generates a corresponding gate and interconnect description. The disadvantage of the behavioral synthesis technique is that in reducing the ASIC to a gate level description, the designer loses significant capability and flexibility to manipulate the ASIC in terms of larger system adjustments since the gate level description only allows for gate level adjustments. Moreover, behavioral synthesis is a longer multi-step complex process requiring two synthesizing steps.
What would be desirable is a single step synthesis process which accepts a higher level (i.e., abstract) description language such as a programming language as its input while avoiding the additional step of reducing a subsequent RTL description to a gate level implementation.
SUMMARY OF THE INVENTION
A system and method of logic synthesis is provided which allows a system designer to go directly from an intuitive algorithm or programming language description of an ASIC to an RTL description and then directly to a synthesized physical implementation of the ASIC, where a one-to-one mapping exists from the RTL description to the physical implementation thereby significantly reducing the design time of the ASIC.
In one embodiment, the system and method of logic synthesis performs a behavioral synthesis on a behavioral description of an ASIC to generate an RTL description. The RTL description is partitioned into RTL sub-descriptions corresponding to each of the control, datapath, and memory portions of the ASIC. The behavioral description can be embodied as a programming language, an algorithm describing a function of an ASIC, kernals of computation in a C program language format (or syntax) within a higher level C program, or a conventional behavi

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