Computer graphics processing and selective visual display system – Computer graphics display memory system – Texture memory
Reexamination Certificate
2002-01-30
2004-09-21
Chauhan, Ulka J. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Texture memory
C345S582000, C345S614000, C345S503000
Reexamination Certificate
active
06795080
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of computer graphics and, more particularly, to high performance graphics systems for rendering graphical objects based on a decomposition of the graphical objects into primitives such as triangles, dots and lines.
2. Description of the Related Art
A graphics system may be configured to receive a stream of graphics parameters defining primitives such as triangles, lines and dots from a host application executing on a host computer. For example, the graphics system may receive a stream of vertices defining triangles in a 3D coordinate space. The triangles represent a collection of 3D objects in the 3D world coordinate space. The graphics system may operate on the triangles to generate a video stream which represents the view of a virtual camera (or virtual observer) in the 3D world coordinate space. In particular, the graphics system may compute color values for each pixel that resides within each triangle (i.e. within the two-dimensional footprint of the triangle in screen space). This process of assigning color values to pixels (or samples) internal to triangles is referred to herein as triangle rasterization.
Triangle rasterization may include the application of one or more textures. In other words, the graphics system may store one or more texture maps in a texture memory and may modify the color of pixels using the one or more texture maps. For example, pixels residing internal to a given triangle comprising part of a wall may be textured with three texture maps, the first map giving the triangle the appearance of brick material, the second map for putting oil smudges on the brick-textured triangle, the third map for varying the level of illumination of pixels on the oil-smudged brick-textured triangle.
According to one conventional rasterization method, each pixel in a given triangle may be textured with all N textures (from the N corresponding texture maps) before proceeding to the next pixel (interior to the triangle) along a scan line or on the next scan line. In other words, a processor may compute color values for a pixel P
1
by sequentially accessing a texel from texture map #1, a texel from texture map #2, . . . , a texel from texture map #N. Then after completing the computation of color values for pixel P
l
, the processor may compute color values for the next pixel P
l+l
interior to the triangle by sequentially accessing a texel from texture map #1, a texel from texture map #2, . . . , a texel from texture map #N. This method of texturing triangles is very inefficient in its use of texture memory as the frequency of cache misses and page misses is large.
Thus, there exists a need for a graphics system and method which could more efficiently apply multiple layers of texture to primitives.
SUMMARY OF THE INVENTION
A graphics system is configured to apply multiple layers of texture information to batches of graphics primitives (e.g. triangles, dots, lines, etc.). In one set of embodiments, the graphics system includes a hardware accelerator, a frame buffer, a video output processor and a texture memory. The texture memory may store multiple layers of texture information.
The hardware accelerator collects primitives into a batch that share a common set of texture layers to be applied. The batch is limited so that the total estimated size (e.g. fragment size or sample size) for the batch is less than or equal to a storage capacity of a texture accumulation buffer. In some embodiments, a fragment size estimate for the batch may be a sum of size estimates for the individual primitives. In other embodiments, the fragment size estimate for a batch may involve an incremental polygon area computation and/or an incremental polygon perimeter computation, especially for a batch of chained primitives (such as a strip or fan). The hardware accelerator stores samples (or fragments) corresponding to the batch primitives in the texture accumulation buffer between the application of successive texture layers.
Because the hardware accelerator operates on a batch of primitives, the large magnitude address jumps between texture layers in the address space of the texture memory may occur less often than if the hardware accelerator cycled through all texture layers per fragment per primitive. Thus, texture accesses to texture memory may be more efficient.
REFERENCES:
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patent: 6480200 (2002-11-01), Fisher et al.
patent: 6483505 (2002-11-01), Morein et al.
patent: 2002/0140703 (2002-10-01), Baker et al.
patent: 2003/0030643 (2003-02-01), Taylor et al.
Watt, Alan, “3D Computer Graphics,” 2000, pp. 227-247.
Kehlet David C.
Lavelle Michael G.
Oberoi Ranjit S.
Ramani Nandini
Wasserman Michael A.
Brightwell Mark K.
Chauhan Ulka J.
Hood Jeffrey C.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Sun Microsystems Inc.
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