Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-27
2004-09-28
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C438S014000
Reexamination Certificate
active
06799311
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for re-organizing a batch or lot of semiconductor wafers based on quality characteristics and/or yield characteristics.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine-tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Generally, a set of processing steps is performed across a group of semiconductor wafers, sometimes referred to as a lot. For example, a process layer that may be composed of a variety of different materials may be formed across a semiconductor wafer. Thereafter, a patterned layer of photoresist may be formed across the process layer using known photolithography techniques. Typically, an etch process is then performed across the process layer using the patterned layer of photoresist as a mask. This etching process results in the formation of various features or objects in the process layer. Such features may be used as, for example, a gate electrode structure for transistors. Many times, trench isolation structures are also formed across the substrate of the semiconductor wafer to isolate electrical areas across a semiconductor wafer. One example of an isolation structure that can be used is a shallow trench isolation (STI) structure.
The manufacturing tools within a semiconductor manufacturing facility typically communicate with a manufacturing framework or a network of processing modules. Each manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which a manufacturing network is connected, thereby facilitating communications between the manufacturing tool and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process.
FIG. 1
illustrates a typical semiconductor wafer
105
. The semiconductor wafer
105
typically includes a plurality of individual semiconductor die
103
arranged in a grid
150
. Using known photolithography processes and equipment, a patterned layer of photoresist may be formed across one or more process layers that are to be patterned. As part of the photolithography process, an exposure process is typically performed by a stepper on approximately one to four die
103
locations at a time, depending on the specific photomask employed. The patterned photoresist layer can be used as a mask during etching processes, wet or dry, performed on the underlying layer or layers of material, e.g., a layer of polysilicon, metal or insulating material, to transfer the desired pattern to the underlying layer. The patterned layer of photoresist is comprised of a plurality of features, e.g., line-type features or opening-type features that are to be replicated in an underlying process layer.
Turning now to
FIG. 2
, a typical flow of processes performed on a semiconductor wafer
105
by a semiconductor manufacturing system is illustrated. The manufacturing system processes at least the portion of a lot of semiconductor wafers
105
(block
210
). Upon processing the semiconductor wafers
105
, the manufacturing system may acquire metrology data regarding the processed semiconductor wafers
105
(block
220
). The manufacturing system may then analyze the metrology data to detect errors associated with the processing of the semiconductor wafers (block
230
). Generally, the manufacturing system then makes a determination whether there are subsequent semiconductor wafers
105
to be processed in the lot (block
240
). If the manufacturing system determines that there are additional semiconductor wafers
105
in the lot to be processed, the wafers from a next set or next portion of the lot are processed and the acquisition of metrology data is then repeated (block
250
). When the manufacturing system makes a determination that there are no additional semiconductor wafers
105
to be processed in the lot, the manufacturing system prepares to process the next lot of semiconductor wafers
105
(block
260
).
Among the problems associated with the current methodology include the uniform characterization of the semiconductor wafers
105
as they are processed throughout a manufacturing facility. In other words, semiconductor wafers
105
within a lot are generally processed in a similar fashion because they are generally characterized uniformly. This methodology may not take into account inherent variations relating to the effects of processing the semiconductor wafers
105
, which may cause different semiconductor wafers
105
to have different characteristics, such as different temperature reactions on different semiconductor wafers
105
. Many times a few semiconductor wafers
105
with poor characteristics may cause the overall average of a parameter associated with a particular characteristic to degrade to the point that the few good semiconductor wafers
105
surrounded by sub par semiconductor wafers
105
may become over-compensated or over-corrected (e.g., some semiconductor wafers
105
being over-polished because the average thickness was calculated to be tool high). Over-compensating/over-correcting generally refers to a semiconductor wafer
105
being subjected to compensation processes due to the fact that a control system mistakenly perceives that there are large errors present on the semiconductor wafer
105
.
For example, if a small percentage of a lot of semiconductor wafers
105
are determined to have, for example, a gate insulation layer that has an out-of-tolerance thickness, then the entire lot of semiconductor wafers
105
may be correlated to a particular electrical characteristic. However, the semiconductor wafers
105
in the lot that have gate insulation layers of the proper thickness may be unnecessarily subjected to compensation processes due to the fact that a larger number of semiconductor wafers
105
in the lot may have a large or an excessively small film-thickness value. Generally, an average is calculated for the particular lot and compensation or correction is made in response to the average calculation. This may cause the properly processed semiconductor wafers
105
to be undesirably subjected to correction processes or procedures that are not necessary for the properly processed semiconductor wafers
105
. In turn, this causes further inefficiency in the processing of semiconductor wafers
105
.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for performing a batch organization of semiconductor wafers. Metrology data associated with a processed semiconductor wafer in a lot is acquired. A quality characteristic associated with the processed semiconductor wafer is determined based upon the metrology data. A plurality of semiconductor wafers associated with the lot are re-organized for
Advanced Micro Devices , Inc.
Rossoshek Helen
Williams Morgan & Amerson P.C.
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