Batch erasable nonvolatile memory device and erasing method

Details Batch erasable nonvolatile memory device and erasing method Batch erasable nonvolatile memory device and erasing method

1996-10-31

1997-10-14

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365218, 36510533, G11C 1300

Patent

active

056778686

ABSTRACT:
A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells of said erase unit with a relatively small energy under a relatively small erase reference voltage, or is provided with an automatic erasing circuit for executing these operations.

REFERENCES:
patent: 4903236 (1990-02-01), Nakayama et al.
patent: 5181188 (1993-01-01), Yamaguchi et al.
patent: 5598368 (1997-01-01), Takahashi

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