Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-21
2004-05-25
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S903000
Reexamination Certificate
active
06740937
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention concerns a semiconductor integrated circuit comprised of macrocells prepared in advance, such as gate arrays.
2. Description of Related Art
LSI manufacturing processes are divided into bulk processes, in which transistors, resistances and other elements are formed at prescribed positions on silicon substrate, and wiring processes, in which elements are connected by metal wiring to form circuit functions. In a gate array, the above-mentioned bulk processes are used to form in advance a bulk chip on which are regularly arranged basic cells (also called unit cells) in an array, so that, simply by changing the wiring processes, various logic circuits can be formed.
FIG. 34
shows a bulk chip used to form the input/output circuit of a semiconductor integrated circuit. As shown in
FIG. 34
, in the case of an ordinary gate array, the input/output circuit (hereafter abbreviated to “I/O circuit”)
10
of a semiconductor integrated circuit comprises main driver units
12
a
and
12
b,
and a predriver unit
14
. In one of the main driver units
12
a,
a plurality of P-channel MOS (hereafter “PMOS”) transistors are arranged, and in the other main driver unit
12
b,
a plurality of N-channel MOS (hereafter “NMOS”) transistors are arranged. In the predriver unit
14
are arranged, in an array, a plurality of basic cells, comprising two PMOS and two NMOS transistors. The dimensions (gate width and gate length) of the transistors comprised by the predriver unit
14
are small compared with the dimensions of the transistors comprised by the main driver units
12
a
and
12
b.
FIG. 35
is a mask pattern diagram for a basic cell comprised of conventional semiconductor integrated circuits. As shown in
FIG. 35
, basic cells comprised by the predriver unit
14
comprise PMOS transistors Tr
1
, Tr
2
and NMOS transistors Tr
3
, Tr
4
.
Each transistor is formed on a P-type Si substrate, not shown. PMOS transistors Tr
1
and Tr
2
are formed within an N-well
16
embedded in this substrate. Within this N-well
16
, a P-type semiconductor region
18
is formed, and within this P-type semiconductor region
18
, the active regions
20
of the PMOS transistors Tr
1
, Tr
2
are formed. On top of these active regions
20
are provided two parallel polysilicon film stripes, as the gates G
1
, G
2
of the PMOS transistors Tr
1
, Tr
2
, respectively.
In a region adjacent to this N-well, the active regions
22
of NMOS transistors Tr
3
, Tr
4
are formed. On top of these active regions
22
are provided two parallel polysilicon film stripes, as the gates G
3
, G
4
of the NMOS transistors Tr
3
, Tr
4
, respectively.
In this way, the PMOS transistor Tr
2
and PMOS transistor Tr
1
are juxtaposed, and the NMOS transistor Tr
4
and NMOS transistor Tr
3
are juxtaposed. The gates of these transistors Tr
1
through Tr
4
are mutually parallel. And, the gate G
1
of PMOS transistor Tr
1
and the gate G
3
of NMOS transistor Tr
3
are provided, that is, arranged in a straight line. Similarly, the gate G
2
of PMOS transistor Tr
2
and the gate G
4
of NMOS transistor Tr
4
are provided in a line.
The gate width W
1
of gate G
1
of PMOS transistor Tr
1
, the gate width W
2
of gate G
2
of PMOS transistor Tr
2
, the gate width W
3
of gate G
3
of NMOS transistor Tr
3
, and the gate width W
4
of gate G
4
of NMOS transistor Tr
4
, are all equal, with W
1
:W
2
:W
3
:W
4
=1:1:1:1.
Further, an active region
24
for power supply (VDD) connection is formed adjacent to PMOS transistor Tr
2
within the N-well
16
. Also, a P-type semiconductor region
26
is formed adjacent to NMOS transistor Tr
4
outside the N-well
16
, and in this P-type semiconductor region
26
is formed an active region
28
for a ground (GND) connection.
At both ends of each gate G
1
through G
4
are provided polysilicon films
30
for wiring connections. Each of these polysilicon films
30
is provided in a state of connection with the gates G
1
through G
4
.
FIG. 36
shows an example of the above-mentioned I/O circuit. In the input buffer shown in
FIG. 36A
, an ESD protection circuit
32
and inverters
34
,
36
are connected between the input signal terminal A and the output signal terminal Y. The ESD protection circuit
32
comprises a main driver unit; the inverters
34
and
36
comprise a predriver unit.
In the output buffer shown in
FIG. 36B
, transistors Tr
1
, Tr
2
and inverters
34
,
36
are connected between the input signal terminal A and output signal terminal Y. The transistors Tr
1
, Tr
2
are comprised by the main driver unit, and the inverters
34
,
36
are comprised by the predriver unit.
In the output buffer shown in
FIG. 36C
, transistors Tr
1
, Tr
2
, a two-input NAND circuit (hereafter “2NAND circuit”)
38
, a two-input NOR circuit (hereafter “2NOR circuit”)
40
, and an inverter
34
are connected between the input signal terminal A and enable signal terminal EB, and the output signal terminal Y. The transistors Tr
1
, Tr
2
are comprised by the main driver unit, and the
2
NAND circuit
38
,
2
NOR circuit
40
, and inverter
34
are comprised by the predriver unit.
In this way, in the predriver unit inverters,
2
NAND and
2
NOR circuits are comprised by basic cells. In a gate array, the threshold voltage Vth and delay time Tpd of these circuits are adjusted through the number of transistors of fixed dimensions used to comprise the predriver unit. Next, an example of configuration of an inverter using basic cells is presented.
In FIG.
37
and
FIG. 38
, a first example of configuration of an inverter using basic cells is presented.
FIG. 37
is a drawing of the inverter mask pattern.
FIG. 38
shows a cross-section of the element structure formed by the mask pattern shown in FIG.
37
.
FIG. 38A
is a cross-sectional diagram at the position of the line I—I in
FIG. 37
;
FIG. 38B
is a cross-sectional diagram at the position of the line J—J in FIG.
37
. In
FIG. 38
, insulation layers provided between each layer are omitted.
As shown in
FIGS. 38A and 38B
, an N-well
16
is formed in the P-type Si substrate
72
, and within this N-well
16
is formed a P-type semiconductor region
18
. Within this P-type semiconductor region
18
are formed the active regions
20
of the PMOS transistors Tr
1
and Tr
2
. On top of this active region
20
are provided gates G
1
, G
2
of the PMOS transistors Tr
1
, Tr
2
.
In
FIG. 37
, shading indicating the first and second metal layers denotes areas where the first metal layer and second metal layer overlap. Also in
FIG. 37
, shading indicating first and second through-holes denotes areas where a first through-hole and second through-hole overlap. Here a first through-hole is formed between the first metal layer and the second metal layer; a second through-hole is formed between the second metal layer and the third metal layer.
In this inverter, the gate G
1
of PMOS transistor Tr
1
and gate G
2
of PMOS transistor Tr
2
are connected to the first metal layer
44
via the contacts
42
provided on the polysilicon films used for wiring connections. These gates G
1
and G
2
are electrically connected by the first metal layer
44
, and this first metal layer
44
is connected to the input terminal IN.
Further, the gate G
1
of PMOS transistor Tr
1
and gate G
3
of NMOS transistor Tr
3
are connected to the first metal layer
48
via the contacts
46
provided on the polysilicon films for wiring connections. These gates G
1
, G
3
are electrically connected by the first metal layer
48
.
As shown in
FIG. 38A
, the active region
20
between the gate G
1
of PMOS transistor Tr
1
and gate G
2
of PMOS transistor Tr
2
is connected to the third metal layer
52
via the first and second through-holes
50
. This third metal layer
52
is connected to the active region
24
used for connection to the power supply (VDD).
The other active regions
20
of the PMOS transistors Tr
1
, Tr
2
are connected to the first metal layer
58
via respective contacts
56
. As shown in
FIG. 38B
, the first metal lay
Nadav Ori
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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