Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2000-12-14
2002-10-08
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S781000, C257S761000, C257S737000, C257S762000
Reexamination Certificate
active
06462426
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit packages with bump type contacts. More particularly, the invention relates to package interconnect structures for absorbing stresses introduced to such bumps after these packages are attached to an external substrate, for example.
BACKGROUND
There are a number of conventional processes for packaging integrated circuits. One approach, which is commonly referred to as “flip chip” packaging, generally contemplates forming solder contact bumps (or other suitable contacts) directly on I/O pads formed on an integrated circuit die. The die is then typically attached to an electronic substrate such as a printed circuit board such that the die contacts directly connect to corresponding contacts on the substrate. The solder contact bumps are then reflowed to electrically connect the die to the substrate. A common problem occurs when flip chips are attached to a substrate. The problem is that, the heat generated by the flip chip during operation causes the die and the substrate to expand and/or contract at different rates due to their different coefficients of thermal expansion (CTE). This thermal cycling fatigue subjects the flip chip and its connection to the substrate to fatigue damage that ultimately shortens the useful life of the electronic device.
FIG. 1
is provided to give a better understanding of the damage suffered by flip chips during thermal cycling. Specifically,
FIG. 1
illustrates a side plan, cross-sectional view of a single solder bump contact
100
of a flip chip
102
that is attached to a printed circuit board (PCB)
104
. For purposes of simplicity, only one of the plurality of solder bump contacts
100
of the flip chip
102
is shown. Typically, flip chips contain conductive pads
106
formed on the top surface of the semiconductor die
108
. The conductive pad
106
leads to the electronic circuitry (not shown) integrated within the die
108
. A layer of passivation material
110
is applied such that the top surface of the die
108
is covered and an opening in the passivation material
110
provides exposes an inner portion of the conductive pad
106
. A resilient material layer
112
is then formed over the passivation layer
110
such that an opening in the resilient layer
112
coincides with the opening in the passivation layer
110
, thereby providing access to the conductive pad
106
. A layer of under bump metal (UBM)
114
is then formed within the resilient and passivation layer openings. The solder bump contact
100
is then formed on top of the UBM
114
. The solder bump contact
100
is reflowed in order to be connected to the PCB bond pad
116
. The form of the solder bump contact
100
is dependent upon the size of the UBM
114
and the PCB bond pad
116
since the solder material collects and solidifies on these surfaces. Typically, the PCB bond pad
116
has a diameter of 300 um and the UBM has a diameter of 150 um. As a result, the contact bump
100
is asymmetrically shaped, as it increases in diameter from the UBM
114
towards the PCB bond pad
116
.
Also shown in
FIG. 1
are cracks
118
and
120
, which formed as a result of temperature cycling fatigue. Cracks
118
are shown as initiating near the outer edge of the UBM
114
and propagating through the solder bump contact
100
. Cracks
120
are shown to have initiated near the outer edge of the UBM and propagated inwardly to the surface of the conductive pad
106
, such that the cracks
120
have completely propagated through the resilient material layer
112
and the passivation layer
110
. Generally, cracks propagate through the resilient material layer
112
and the passivation layer
110
faster than through the solder bump
100
since the solder bump material is a more ductile material. The cracks
120
become arrested at the surface of the conductive pad
106
due to the highly ductile properties of the conductive pad
106
. For instance, the conductive pads
106
are often formed of Aluminum. The diameter of the conductive pad
106
is generally formed to be larger than the diameter of the UBM
114
so that the conductive pad
106
can be used to arrest the cracks propagating through the resilient and passivation material layers. A smaller conductive pad
106
would allow the cracks
120
to propagate around and underneath the edges of conductive pad
106
and through the semiconductor die
108
until the entire solder bump contact
100
, together with fragments of the semiconductor die
108
break away from the die
108
. As may be appreciated, the damage illustrated in FIG. I may be caused by factors other than temperature cycling. For instance, vibrations due to external operational conditions may also cause structural damage to the electrical system.
One possible configuration allowing for a more structurally robust flip chip package involves forming a UBM
114
having a larger diameter such that its diameter is approximately equal to the diameter of the PCB bond pad
116
. This may be done, for example, by extending the portion of the UBM
114
covering the resilient material, referred to as the lip
114
a.
This configuration results in a solder bump contact that solidifies, after being reflowed, into a more symmetrical shape. The resulting symmetrical shape of the solder bump contact has respective diameters near the UBM
114
and near the PCB bond pad
116
that are more closely equal to each other, unlike, and in contrast to the asymmetrical shape of the solder bump contact
100
in FIG.
1
. Symmetrically shaped solder contact bumps are more flexible, and therefore absorb and distribute stresses in a manner that more effectively preserves the structural integrity of the flip chip package and PCB. In order to fabricate semiconductor devices having larger UBMs, the underlying and supporting conductive pads
106
must also be enlarged so that the crack arresting ability of the conductive pads is utilized. Unfortunately, however, increasing the diameter of the conductive pads
106
reduces the number of integrated circuits that may be fabricated within the semiconductor die since the larger conductive pads
106
must occupy more of the limited semiconductor surface area. Ultimately, this flip chip configuration is able to increase its structural integrity only at the expense of reduced functionality.
In view of the foregoing, an improved flip chip design would be desirable such that upon connection to an electronic substrate, the flip chip exhibits structurally robust properties without sacrificing the flip chip's degree of functionality.
SUMMARY
The present invention pertains to bumped-type semiconductor devices designed to have structurally robust characteristics without sacrificing the device's degree of functionality. The integrated circuit device of the present invention includes a semiconductor die having a plurality of conductive pads. Over the conductive pads is formed a passivation layer that has a plurality of passivation layer openings. At least one of the passivation layer openings are each positioned over an associated one of the conductive pads. Barrier base pads are placed in electrical contact with the conductive pads such that a portion of each of barrier base pads cover at least the perimeter of each passivation layer opening thereby preventing cracks from propagating through the integrated circuit device.
In another aspect of the invention, the integrated circuit device is attached to an external substrate by connecting the contact bumps to the bond pads on an electronic substrate.
In yet another aspect of the invention, a method for manufacturing the integrated circuit device using the inventive barrier base pad is described.
These and other features and advantages of the present invention will be presented in more detail in the following specification of the invention and the accompanying figures which illustrate by way of example the principles of the invention.
REFERENCES:
patent: 5629564 (1997-05-01), Nye, III et al.
patent: 5656858 (1997-08-01), Kond
Gee Stephen A.
Kelkar Nikhil Vishwanath
Beyer Weaver & Thomas LLP
Lee Eddie
National Semiconductor Corporation
Nguyen Joseph
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