Barrier for use in 3-D integration of circuits

Details Barrier for use in 3-D integration of circuits Barrier for use in 3-D integration of circuits

2008-05-27

2008-05-27

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S599000, C438S618000, C438S639000, C438S656000, C257SE21584

Reexamination Certificate

active

11278042

ABSTRACT:
A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.

REFERENCES:
patent: 5640049 (1997-06-01), Rostoker et al.
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patent: 6656748 (2003-12-01), Hall et al.
patent: 6764950 (2004-07-01), Noguchi et al.
patent: 7176128 (2007-02-01), Ahrens et al.
patent: 2005/0054122 (2005-03-01), Celii et al.
Craig Keast, et al., MIT Lincoln Laboratory's 3D Circuit Integration Technology, Apr. 13, 2004, SEMATECH 3D Technology, Modeling and Process Symposium.

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