Barrier and landing pad structure in an integrated circuit

Details Barrier and landing pad structure in an integrated circuit Barrier and landing pad structure in an integrated circuit

1996-09-06

1998-08-11

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257754, 257755, 257757, H01L 2348

Patent

active

057931119

ABSTRACT:
A method is provided for forming an improved landing pad with barrier of a semiconductor integrated circuit, and an integrated circuit formed according to the same. An opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a silicide layer disposed over a barrier layer which is disposed over a polysilicon layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. The barrier layer, formed as part of the landing pad, will provide for a uniform and high integrity barrier layer between the diffused region and an overlying aluminum contact to prevent junction spiking. A second dielectric having an opening therethrough is formed over the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will connect with the diffused region through the landing pad. Misalignment of the conductive contact opening may be tolerated without invading design rules.

REFERENCES:
patent: 4441247 (1984-04-01), Gargini et al.
patent: 4707457 (1987-11-01), Erb
patent: 4789885 (1988-12-01), Brighton et al.
patent: 4810666 (1989-03-01), Taji
patent: 4822449 (1989-04-01), Flanner et al.
patent: 4844776 (1989-07-01), Lee et al.
patent: 4851895 (1989-07-01), Green et al.
patent: 4868138 (1989-09-01), Chan et al.
patent: 4908332 (1990-03-01), Wu
patent: 4916397 (1990-04-01), Masuda et al.
patent: 4922311 (1990-05-01), Lee et al.
patent: 4984056 (1991-01-01), Fujimoto et al.
patent: 4997790 (1991-03-01), Woo et al.
patent: 5036383 (1991-07-01), Mori
patent: 5071783 (1991-12-01), Taguchi et al.
patent: 5110752 (1992-05-01), Lu
patent: 5158910 (1992-10-01), Cooper et al.
patent: 5210429 (1993-05-01), Adan
patent: 5219789 (1993-06-01), Adan
patent: 5229326 (1993-07-01), Dennison et al.
patent: 5247199 (1993-09-01), Matlock
patent: 5275972 (1994-01-01), Ogawa et al.
patent: 5298463 (1994-03-01), Sandhu et al.
patent: 5298792 (1994-03-01), Manning
patent: 5308795 (1994-05-01), Hawley et al.
patent: 5316976 (1994-05-01), Bourg, Jr. et al.
patent: 5359226 (1994-10-01), DeJong
patent: 5420058 (1995-05-01), Lee et al.
patent: 5514622 (1996-05-01), Bornstein et al.
Broadbent, et al., "Selective Low Pressure Chemical Vapor Deposition of Tungsten," J. Electrochem. Soc.: Solid-State Science and Technology, vol. 131, No. 6, Jun. 1984, pp. 1427-1433.
G. Queirolo, et al., "Dopant Activation, Carrier Mobility, and TEM Studies in Polycrystalline Silicon Films," J. Electrochem. Soc., V. 137, No. 3, Mar. 1990, pp. 967-970.
C.S. Pai, et al., "Chemical Vapor Deposition of Selective Epitaxial Silicon Layers," J. Electrochem. Soc., V. 137, No. 3, Mar. 1990, pp. 971-976.
M. Cleeves, et al., "A Novel Disposable Post Technology for Self-Aligned Sub-Micron Contacts," 1994 IEEE, 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 61-62.

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