Barbed vias for electrical and mechanical connection between...

Details Barbed vias for electrical and mechanical connection between... Barbed vias for electrical and mechanical connection between...

2000-12-28

2003-09-02

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S687000

Reexamination Certificate

active

06613664

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the fabrication of semiconductor devices, and more particularly to via formation in multi-layer integrated circuits.
BACKGROUND OF THE INVENTION
Semiconductors are widely used for integrated circuits for electronic applications, including radios, televisions and personal computing devices, as examples. Such integrated circuits typically use multiple transistors fabricated in single crystal silicon. It is common for there to be millions of semiconductor devices on a single semiconductor product. Many integrated circuits now include multiple levels of metallization for interconnections.
The semiconductor industry continuously strives to decrease the size of the semiconductor devices located on integrated circuits. Miniaturization is generally needed to accommodate the increasing density of circuits necessary for today's semiconductor products. In the past, the material typically used to isolate conductive leads from each other has been silicon dioxide; however, the dielectric constant (k) of silicon dioxide deposited by chemical vapor deposition is on the order of 4.1 to 4.2. The dielectric constant is based on a scale where 1.0 represents the dielectric constant of a vacuum. Silicon dioxide provides a minimal thermal expansion coefficient mismatch with conductive layer materials, and is a strong material.
Low-k materials (e.g., having a dielectric constant of 3.6 or less) are now being used for the insulating material separating conductive layers and metal leads of semiconductor devices in order to reduce the capacitive coupling between interconnect lines. Widely used low-k materials comprise organic spin-on materials, which must be heated to remove the liquid, or solvent. Often these low-k materials have a high thermal expansion coefficient compared to metals and silicon dioxide.
Semiconductor wafers are frequently temperature-cycled during fabrication due to the nature of the manufacturing process. When a device comprises multiple metallization and dielectric layers, the solvent-removing heating step for the low-dielectric constant material layers must be repeated numerous times (e.g., each layer must be cured), which can be problematic, especially for the lower layers of the device. The mismatch of thermal expansion coefficients of metal leads and low-k dielectric layers causes thermo-mechanical stress, leading to increased resistances, delaminations, electrical intermittencies and opens, resulting in reduced yields.
What is needed in the art is an interconnect structure and fabrication method thereof that can withstand the thermal cycling required for processing multi-layer semiconductor devices having a low-k insulating material between conductive layers.
SUMMARY OF THE INVENTION
These problems are generally solved or circumvented by the present invention, which achieves technical advantages as a barbed via structure and method of fabrication thereof that provides strength, robustness and stabile electrical resistance to metal interconnect layers of a multi-layer semiconductor device.
Disclosed is a method of interconnecting conductive layers in a multi-layer integrated circuit, the integrated circuit comprising a first conductive line in a first dielectric layer and a second conductive line in a second dielectric layer, the second conductive line and second dielectric layer residing over the first conductive line and first dielectric layer, respectively. The method comprises depositing a second dielectric layer over the first conductive line and the first dielectric layer, and forming a via opening over the first conductive line in the second dielectric layer. In the second dielectric a trench for the second conductive line and the via opening are formed by subsequent patterning steps, in a dual damascene approach. The via may be formed first and trench second or alternatively, the trench may be formed first and the via formed second. A barb opening is formed in a top portion of the first conductive line, the barb opening having a region extending beneath the second dielectric layer. The via opening, the barb opening and the trench opening for the second conductive line are filled with a conductive material to form a barbed via with a conductive line on top, wherein the barbed via provides electrical connection between the first conductive line and the second conductive line.
Also disclosed is a method of manufacturing interconnect layers of a multi-layer integrated circuit in a single damascene approach, comprising forming a first conductive line in a first dielectric layer, depositing a second dielectric layer over the first conductive line and the first dielectric layer, and forming a via opening over the first conductive line in the second dielectric layer. A barb opening is formed in a top portion of the first dielectric line, the barb opening having a region extending beneath the second dielectric layer. The via opening and the barb opening are filled with a conductive material to form a barbed via, and a third dielectric layer is deposited over the barbed via and the second dielectric layer. A second conductive line is formed in the third dielectric layer over the barbed via.
Further disclosed is an interconnect structure for a multi-layer integrated circuit, comprising a first conductive line formed in a first dielectric layer, a second dielectric layer deposited over the first dielectric layer and the first conductive line, and a barbed via formed in the second dielectric layer over the first conductive line. The barbed via has a barbed portion extending into a top portion of the first conductive line, with the barbed portion having a portion extending beneath the first conductive line. A third dielectric layer is deposited over the second dielectric layer and the barbed via, and a second conductive line is formed in the third dielectric layer above the barbed via (single damascene approach) or alternatively the second conductive line may be realized in the second dielectric layer and filled together with the barbed via by the same deposition steps of the conductive liners, seed layers and metal fills (dual damascene approach).
Advantages of the invention include preventing delamination, breakage and opens from occurring during thermal expansion in multi-level interconnect structures due to materials having different thermal expansion coefficients. The barbed vias of the present invention provide a sturdy, robust, structure that can withstand the thermal cycling during the multiple times a wafer is exposed to high temperatures in order to cure low-dielectric constant insulating materials and during other processing steps. The invention results in improved yields and lowered electrical resistance value of vertical connections within the wafer.


REFERENCES:
patent: 5354712 (1994-10-01), Ho et al.
patent: 5470790 (1995-11-01), Myers et al.
patent: 6159851 (2000-12-01), Chen et al.
patent: 6218283 (2001-04-01), Park et al.

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