Banked SRAM device with bit line refresh

Details Banked SRAM device with bit line refresh Banked SRAM device with bit line refresh

1995-12-29

1997-06-24

Dinh, Son T.

Static information storage and retrieval

Addressing

Plural blocks or banks

36518907, 365203, 365204, 365236, G11C 700

Patent

active

056423241

ABSTRACT:
A data storage device is provided. The data storage device, which is coupled to a data processing device, includes a memory array partitioning into a plurality of memory banks. The data storage device further includes a bank enable circuit for enabling at least one of the memory banks from the plurality of memory banks of the memory array. The data storage device also includes an operation/pseudooperation enable circuit (OPEC) for generating an operation or a pseudooperation signal to one or more banks enabled by the bank enable circuit. The OPEC has a first input for receiving an operation request signal from the data processing device and a second input. Additionally the data storage device includes a pseudooperation control circuit for controllably generating a pseudooperation request signal to the bank enable circuit and to the second input of the OPEC.

REFERENCES:
patent: 5260904 (1993-11-01), Miyawaki et al.
patent: 5274597 (1993-12-01), Ohbayashi et al.
patent: 5299167 (1994-03-01), Yano
patent: 5301163 (1994-04-01), Reinschmidt et al.

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