Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-09-23
2001-08-14
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S129000, C711S005000, C365S185110, C365S185130
Reexamination Certificate
active
06275894
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a flash memory device, and more particularly, to a simultaneous operation flash memory device with a flexible bank partition architecture.
BACKGROUND ART
Non-volatile flash memory devices have been developed by the semiconductor integrated circuit industry for various applications such as computers and digital communications. A conventional non-simultaneous operation flash memory device typically includes a single fixed memory bank. A conventional simultaneous operation flash memory device typically comprises two fixed memory banks each comprising a fixed number of sectors of memory cells. Each sector of memory cells has a fixed amount of memory storage, for example, 0.5 megabytes (MB), and consists of a fixed number of pages of memory cells, for example, 16 pages of memory cells. A page is typically defined as one word of memory stored in the memory cells on a single word line.
In a conventional simultaneous operation flash memory device, for example, a conventional simultaneous operation NOR flash memory array, the NOR memory cells are divided into an upper memory bank and a lower memory bank each having a fixed size of memory storage. The upper and lower memory banks are typically used for different functions. For example, the upper memory bank may be used for code storage, whereas the lower memory bank may be used for data storage. Because the upper and lower bank memory partitions are fixed in conventional simultaneous operation flash memory devices, different simultaneous operation flash memory devices with different integrated circuit designs are required for different memory partitions. Therefore, in order to suit a variety of applications which may require different partitions of the upper and lower memory banks for code and data storage, new circuit designs would be required for different applications.
Because the size of memory storage in each of the upper and lower banks is not variable in a conventional simultaneous operation flash memory device, a single circuit design for a conventional simultaneous operation flash memory device may be suitable for only one of several different applications in which different partitions of the upper and lower memory banks are required. In order to produce simultaneous operation flash memory devices with different partitions of the upper and lower memory banks, a different circuit design and a full set of different masks are required for each of the devices. A disadvantage of having to design a different integrated circuit and a full set of different masks for each of the simultaneous operation flash memory devices with different upper and lower bank memory partitions is that the design, fabrication and testing processes can be very costly and time consuming. Therefore, there is a need for a simultaneous operation flash memory device with a flexible bank partition architecture. Furthermore, there is a need for a bank selector circuit for selecting the upper and lower memory banks in a simultaneous operation flash memory device with a flexible bank partition architecture in response to a memory address input.
DISCLOSURE OF THE INVENTION
The present invention satisfies these needs. In accordance with the present invention, a bank selector circuit for a simultaneous operation memory device with a flexible bank partition architecture generally comprises:
(a) a memory boundary option designating a memory partition boundary selected from a plurality of predetermined memory partition boundaries, the memory boundary option capable of generating a partition boundary indicator signal based upon the selected memory partition boundary;
(b) a bank selector encoder, coupled to the memory boundary option, capable of generating a plurality of code bits of a bank selector code based upon a partition of memory into an upper memory bank and a lower memory bank at the memory partition boundary in response to receiving the partition boundary indicator signal; and
(c) a bank selector decoder coupled to receive the bank selector code from the bank selector encoder and further coupled to receive a plurality of memory address bits of a memory address, the decoder having a bank selector output capable of signifying whether the memory address belongs to the upper memory bank or the lower memory bank.
In an embodiment, the memory boundary option comprises a plurality of memory partition boundary indicator terminals capable of outputting a partition boundary indicator signal. In a further embodiment, the bank selector encoder comprises a read-only memory (ROM) array coupled to the partition boundary indicator terminals of the memory boundary option and capable of outputting a bank selector code in response to receiving the partition boundary indicator signal from the respective partition boundary indicator terminals. A unique bank selector code is generated by the bank selector encoder for each of the predetermined memory partition boundaries which can be designated by the memory boundary option.
In yet a further embodiment, the decoder comprises a logic bit P determining circuit coupled to receive a first plurality of the bank selector code bits and a first plurality of the memory address bits, a logic bit Q determining circuit coupled to receive a second plurality of the code bits and the first plurality of the memory address bits, and a logic bit O determining circuit coupled to receive a third one of the bank selector code bits and a second plurality of the memory address bits. The bank selector decoder further comprises an output logic circuit coupled to the logic bit O, P and Q determining circuits to generate a single-bit bank selector output signal to signify whether the memory address belongs to the upper memory bank or the lower memory bank.
In an embodiment, the output logic circuit comprises an AND gate and a NOR gate. The AND gate has first and second AND gate inputs and an AND gate output, the first and second AND gate inputs connected to the logic bit P and Q determining circuits, respectively. The NOR gate has first and second NOR gate inputs and a NOR gate output, the first and second NOR gate inputs connected to the logic bit O determining circuit and to the AND gate output, respectively. The NOR gate output generates the bank selector output signal.
In a further embodiment, the partition indicator circuit further comprises upper and lower bank conductive line segments coupled to the respective inputs of a plurality of NOR gates, the outputs of which form the respective partition boundary indicator terminals. In an additional embodiment, the logic bit O, P and Q determining circuits each comprise a plurality of p-channel metal oxide semiconductor (PMOS) and n-channel MOS (NMOS) transistors coupled to receive at least some of the memory address inputs and the bank selector code bits, with the outputs of the logic bit O, P and Q determining circuits coupled to the output logic circuit.
Advantageously, the present invention provides a bank selector circuit for selecting the upper or lower memory bank in a simultaneous operation flash memory device with a flexible bank partition architecture based upon the memory partition boundary in response to receiving a memory address. The present invention allows a simultaneous operation flash memory device with a flexible bank partition architecture to be realized without the costs and efforts associated with designing different circuits and preparing different sets of masks for meeting the requirements of different memory bank sizes to produce different conventional simultaneous operation flash memory devices with fixed upper and lower bank partitions.
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patent: 0 741 3
Buskirk Michael Van
Chen Johnny
Kasa Yasushi
Kuo Tiao-Hua
Leong Nancy
Advanced Micro Devices , Inc.
Fliesler Dubb Meyer & Lovejoy LLP
Kim Matthew
Peugh Brian R.
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