Bank selectable Y-decoder circuit and method of operation

Details Bank selectable Y-decoder circuit and method of operation Bank selectable Y-decoder circuit and method of operation

1998-12-10

1999-12-21

Dinh, Son T.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, G11C 800

Patent

active

060058226

ABSTRACT:
Bank selectable Y-decoder circuit (24) generates a plurality of Y-select signals (60, 62, 64, 66) for addressing columns of a plurality of memory banks (12, 14) in a memory array (10) and includes a high-order column factors decode circuit (34) for receiving a plurality of column factor signals. A first low-order column factor circuit (30) generates a first set of Y-select signals (60, 62) for addressing at least one column of a first set of memory banks (12). A second low-order column factors circuit (32) generates a second set of Y-select signals (64, 66) for addressing at least one column of a second set of memory banks (14). The result is a Y-decoder circuit (24) that consumes less silicon die area, without a reduction in circuit performance.

REFERENCES:
patent: 5483497 (1996-01-01), Mochizuki et al.
patent: 5579280 (1996-11-01), Son et al.
patent: 5596543 (1997-01-01), Sakui et al.
patent: 5802006 (1998-09-01), Ohta et al.

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