Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1999-01-04
2002-06-04
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S005000, C365S201000
Reexamination Certificate
active
06401180
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to controlling memories and more particularly to scheduling of precharge operations on memories.
2. Description of the Related Art
Access to memory is a critical performance criteria in computer systems. Access prediction has been employed in high performance processor design to improve memory access performance. In such applications, processing efficiency is improved by dynamically predicting whether a conditional branch instruction will result in the branch being taken (discontinuous instruction fetch access) or in the branch not being taken (continuous instruction fetch access). However, such access prediction is limited to processors and typically to the occurrence of branch instructions and does not generally provide improved access to main system memory.
In computer systems, the main memory is typically composed of dynamic random access memory (DRAM) organized in banks as shown in FIG.
1
. Typically, the high order portion of row address bits
10
are used to select the appropriate bank for each memory access. Within each bank, additional row address bits are used to select a specific row within each bank. The column address bits are supplied to each bank to select the columns within the bank that are being read. As is known in the art, between read accesses to a bank, a precharge operation takes place in the memory array to place the array in a state which allows the sense amplifiers to sense the values stored in the memory. In conventional DRAMs, those precharge operation are necessary in order to access a different row in the bank and are accomplished by bringing the row access strobe (RAS) inactive. In some current DRAMs such as the RAMBUS DRAM, precharge commands are provided to the DRAM. The precharge commands cause the selected bank to prepare the associated sense amplifiers so that a different row in that bank can be accessed.
It is known in the art that if the same row in a bank is being sequentially accessed, i.e., only the column bits are changing for the sequential access, the memory access can be performed without the time penalty of the precharge operation and without providing a new row address, and incurring a read access delay from the memory array.
Memory controllers have therefore adopted various approaches to precharge operations in order to maximize the throughput of the memory depending on the nature of the memory accesses. Memory controller
12
may be designed or programmed to perform memory bank pre-charge after each memory access. That approach would be desirable when the memory access pattern is highly random with frequent row misses. However, for highly localized access patterns with frequent row hits, the memory controller would have better performance by precharging only prior to an access of a different row of the bank.
In order to improve memory access performance, it would be desirable to have a memory controller that dynamically chooses between various approaches to precharge operations.
SUMMARY OF THE INVENTION
Accordingly, it has been discovered to provide a bank history table and associated control logic that allows the memory controller to dynamically choose either to precharge immediately after an access or to delay precharge, the choice being based on history bits indicating whether previous memory accesses were row hits or misses. The history bits are stored in the bank history table. A dynamic choice based upon access history can increase the probability of making a correct choice, that is, a choice that minimizes access response time.
In one embodiment, the invention provides an integrated circuit that includes a bank history table having a plurality of memory access history vectors. Each of the memory access history vectors corresponds to a respective one of a plurality of banks of memory. A precharge decision circuit, which is coupled to the bank history table, receives a selected one of the history vectors and a new history bit. The precharge decision circuit makes a precharge decision for the memory using the selected one of the memory access vectors and the new history bit. The new history bit is generated by comparing for equality the row number of the current row being accessed with a stored value of the last row accessed for that bank.
In another embodiment, the invention provides a method for providing a precharge decision for a memory having a plurality of banks of memory. The method includes providing a bank history table having a plurality of memory access history vectors corresponding to a respective one of the banks of memory. One of the memory access history vectors is provided to a precharge decision circuit according to a current bank address. The precharge decision circuit makes the precharge decision using the history vector provided.
REFERENCES:
patent: 5813038 (1998-09-01), Thome et al.
patent: 5873114 (1999-02-01), Rahman et al.
patent: 6005592 (1999-12-01), Koizumi et al.
patent: 6052756 (2000-04-01), Barnaby et al.
Rambus (Advance Information), “Direct RAC Data Sheet”, Aug. 7, 1998, pp. 1-46.
Direct Rambus (Technology Disclosure), “1.6 GM/memory sec”, Oct. 1997, pp. 1-16.
Rambus (Advance Information), “Direct RDRAM 256/288-Mbit (512K×16/18×32s)”, Sep. 4, 1998, pp. 1-62.
Advanced Micro Devices , Inc.
Anderson Matthew D.
Kim Matthew
Zagorin O'Brien & Graham LLP
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