Bank conflict avoidance in multi-bank DRAMS with shared...

Details Bank conflict avoidance in multi-bank DRAMS with shared... Bank conflict avoidance in multi-bank DRAMS with shared...

2000-07-14

2002-04-23

Lane, Jack A. (Department: 2185)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S203000, C711S210000, C711S217000, C365S230030

Reexamination Certificate

active

06378032

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to data transfers to or from a DRAM and, more particularly, to data transfers involving a multi-bank DRAM that utilizes shared sense amplifiers.
BACKGROUND OF THE INVENTION
Many conventional DRAM devices utilize shared sense amplifier architectures. A typical example is a DRAM having a plurality of separate memory banks, each of which shares sense amplifiers with two adjacent memory banks. For example, half of bank n shares sense amplifiers with half of bank n−1, and the other half of bank n shares sense amplifiers with half of bank n+1. Due to this shared sense amplifier architecture, when bank n is open, a subsequent access to a different row in bank n, or to any row in bank n−1 or bank n+1, cannot be started without first closing bank n. If such a subsequent access is attempted before bank n is closed, a bank conflict occurs.
In some exemplary DRAMs having shared sense amplifier architectures, for example, in Direct RDRAMs produced according to the RDRAM specification from Rambus, all data transfers to the DRAM from an external source or from the DRAM to an external destination are performed in blocks of 128 bytes. In a typical bank access cycle, either 16 or 32 bytes from the memory bank can be accessed. Thus, a 128 byte transfer can be performed, for example, by 8 accesses of 16 bytes or 4 accesses of 32 bytes. However, bank conflicts as described above can cause stalls to occur (waiting for a bank to close) during the 128 byte data transfer, thus disadvantageously degrading data bus utilization (i.e., increasing data bus latency) during the data transfer.
It is therefore desirable to provide for accessing multiple banks of a shared sense amplifier DRAM during a data transfer (or a plurality of consecutive data transfers) without bank conflicts and the associated stalls.
The present invention permits consecutive data transfers, each involving accesses of multiple DRAM banks, to be performed without any bank conflict-related stalling between or within transfers. In particular, the invention identifies groups of banks, each group including a plurality of constituent banks that can be sequentially accessed during a given data transfer without conflicting with one another. Each data transfer sequentially accesses the banks of one of the groups. The invention also provides for selectively reordering the sequence in which the banks of a given group will be accessed during a data transfer. This reordering can prevent conflicts with banks accessed during prior or subsequent data transfers.


REFERENCES:
patent: 6144577 (2000-11-01), Hidaka

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