Bank address mapping according to bank retention time in...

Details Bank address mapping according to bank retention time in... Bank address mapping according to bank retention time in...

2005-07-19

2005-07-19

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S005000, C711S158000, C711S165000, C711S202000

Reexamination Certificate

active

06920523

ABSTRACT:
A system and method for refreshing data in a dynamic random access memory (“DRAM”) is provided, where the system includes a data memory having a plurality of memory banks, a map memory in signal communication with the data memory for translating an internal address of each of the plurality of memory banks into a corresponding external address, a map comparator in signal communication with the map memory for selectively enabling a memory bank in accordance with its external address, a refresh address generator in signal communication with the map comparator for selectively refreshing the enabled memory bank in accordance with its external address, and a refresh counter in signal communication with the refresh address generator for signaling a refresh in accordance with the maximum required refresh time of the enabled memory bank; and where the corresponding method includes determining the maximum required refresh period for each of the memory banks, respectively, prioritizing the memory banks in accordance with their respective refresh periods, utilizing the memory banks in order of their respective prioritizations, selectively disabling at least one of the memory banks in reverse-order of their respective prioritizations, and refreshing only the remaining non-disabled memory banks.

REFERENCES:
patent: 6446159 (2002-09-01), Kai et al.
patent: 6557072 (2003-04-01), Osborn
patent: 2003/0028711 (2003-02-01), Woo et al.

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