Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2006-06-20
2006-06-20
Anderson, Matthew D. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S171000, C711S172000, C710S033000, C710S038000, C710S057000
Reexamination Certificate
active
07065623
ABSTRACT:
Methods, system and computer program product are provided to improve the efficiency of data transfers in a PPRC environment. A block of data to be transferred is divided into tracks. Each track is allocated to a data mover task control block (TCB) with a master TCB being assigned to supervise the data mover TCBs. The tracks are then transferred from the primary storage controller to the secondary controller in a piped fashion over a link coupling the primary and secondary storage controllers. However, the usage of resources is monitored by a resource management algorithm and, if too many TCBs are being used for a transfer or if the supply of data mover TCBs is exhausted, the transfer is automatically switched to a serial, non-piped transfer with the master TCB serving as the data mover TCB for the remaining tracks. In addition, the various links coupling the primary and secondary storage controllers is monitored to determine which link will provide the fastest transfer. If, during a transfer of tracks over one link, a faster link is identified, the transfer may be switched to the second, faster link.
REFERENCES:
patent: 4445176 (1984-04-01), Burk et al.
patent: 5892925 (1999-04-01), Aditya et al.
patent: 6920537 (2005-07-01), Ofek et al.
Chen James C.
Gluck Olympia
Lin Edward H.
Stanley Warren K.
Walder Gabriel G.
Anderson Matthew D.
Dare Ryan A.
Shifrin Dan
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