Bandwidth reduction for rendering using vertex data

Details Bandwidth reduction for rendering using vertex data Bandwidth reduction for rendering using vertex data

2005-09-27

2005-09-27

Bella, Matthew C. (Department: 2676)

Computer graphics processing and selective visual display system

Computer graphics display memory system

Addressing

C345S418000, C345S539000

Reexamination Certificate

active

06950108

ABSTRACT:
Embodiments of the present invention provide a split vertex buffer where the data for each vertex is split between parallel vertex buffers. The first buffer contains vertex X and Y data, while the second parallel buffer contains the remainder of the vertex data. Given the split vertex buffers, the hardware binning-engine is now permitted to read and cache only vertex screen X and Y data. Especially given a typically high level of temporal coherency between indexed vertex references, the reading and caching of large parcels of vertex screen-space X and Y leads to lower and highly efficient utilization of memory bandwidth for hardware binning input. Embodiments of the present invention thus reduce the hardware binning memory bandwidth requirements and improve memory utilization.

REFERENCES:
patent: 5696944 (1997-12-01), Krech, Jr.
patent: 6344852 (2002-02-01), Zhu et al.
patent: 6369813 (2002-04-01), Pentkovski et al.
patent: 6535209 (2003-03-01), Abdalla et al.
patent: 2003/0122838 (2003-07-01), Doyle et al.

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