Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-11-05
2004-12-28
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S165000, C711S170000
Reexamination Certificate
active
06836823
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system and method for enhancing the bandwidth utilization for uncached devices in a computer system, and more particularly, the invention relates to a system and method for maximizing the utilization of the available bandwidth for a reconfigurable processor incorporated within a computer system.
2. Discussion of the Related Art
Modern microprocessors are designed to maximize their performance through the use of cache memory located very closely to the processor core. A cache memory stores a subset of the most recently and frequently used contents of a computer system's main memory. Cache memories can provide data to microprocessors much faster than main memory. This is so for several reasons. The memory cache is often made of higher quality memory circuits than the main memory. These high-end circuits can simply operate at a higher clock rate than the main memory. In addition, there may also be a dedicated bus between the microprocessor and the cache memory that results in higher bandwidth between the microprocessor and the main memory. Finally, to take advantage of temporal locality, a cache memory is physically located much closer to the microprocessor than main memory, and in some cases is integrated on the same circuit as the microprocessor.
By first accessing the cache memory, as opposed to more physically distant main memory, the microprocessor reduces its memory access latency and accelerates its processing throughput. Only when an item is not found in the cache does the microprocessor need to retrieve it from main memory and place it in the cache for future use. When a particular piece of data is accessed, it is very likely that nearby units of data will also be accessed shortly. To take advantage of this spatial locality, a block of data larger than is currently needed is generally written into the cache when main memory is accessed. Cache memory is typically organized as rows of data, wherein each row is the length of the data block fetched from memory. Each of these rows is known as a cache line. Each fetch from memory returns the same cache line width size block of data. For efficiency, each bus that interacts with the cache does so on a cache line basis. In other words, all data transfers are done in the cache line size.
Using cached memory poses problems in a microprocessor-based system that also contains devices associated with the memory subsystem that are not normal memory chips. One such example is a reconfigurable processor such as SRC's Multi-Adaptive Processor (“MAP”) units. These MAP units decode normal memory addresses into commands that the reconfigurable logic will execute. Such command sets will, among other things, contain commands to write operands to the first-in/first-out receive queue (“receive FIFO”) on the MAP, as well as read results from a first-in/first-out output queue (“output FIFO”) located on the MAP.
Due to reductions in a processor's efficiency, as well as the limitations of an uncached device's ability to use cache line sized data, it is necessary to permit the read and write requests to bypass the cache and go directly to where the uncached device resides. Fortunately, most microprocessors will allow for uncached memory references that will do just that. These uncached memory references, however, require a response from the uncached device before the next transaction can by issued. In uncached mode the processor will send a read request, for example, directly to the main memory and wait for the appropriate response. In a large system this response may take time equal to several microprocessor transaction periods. For this reason microprocessors will have an execution queue that allows it to initiate multiple transactions to different addresses before the response to the first transaction is received. This method maximizes the input/output bandwidth of the microprocessor.
If the microprocessor is attempting to read the results stored in an output FIFO, as is the case with a MAP, the address that is decoded into the MAP READ command would be requested by the processor. This address correlates to the front end of the output FIFO of the MAP, which does not change no matter how long or short the output FIFO might be. However, because any subsequent MAP READ command will attempt to access the same address, the microprocessor will not issue a second MAP READ command until a response from the first command is received, regardless of the depth of the microprocessor's execution queue. Waiting for a response significantly reduces the efficiency of the processor's use of the available resources.
The reason for this delay is that as the microprocessor program is executing, and because the cache has been bypassed, the microprocessor sees that the address for the second main memory access is the same as the first. In this situation the microprocessor is aware that it already has an outstanding request to that address and must halt any further use of that address until the first response is received.
A similar issue arises during a write command to an uncached device. An uncached device is typically unable to handle a full cache line of data. In the case of a MAP, the commands to be written to the MAP can be even shorter than the amount of data capable of being transferred to an uncached device. Reading from memory for each of these data elements significantly reduces the efficiency with which the computer system transfers data. Writing a full line of data creates an additional burden for the MAP unit.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a system and method for enhancing the utilization of the available bandwidth for an uncached device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a system and method for efficiently utilizing the bandwidth for an uncached memory read request.
Another object of the present invention is to provide a method for efficiently utilizing the bandwidth for an uncached memory write request.
Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In one embodiment, the invention comprises a method for writing data to an uncached device within a computer system, comprising the steps of receiving by a processor a request to write data to an uncached device, requesting the data by the processor, receiving the data by the processor, striding a section of the data into an optimized number of successive cache line addresses in the uncached device address space, and writing the successive cache line addresses to the uncached device.
In a further embodiment, the invention comprises a method for reading data from an uncached device within a computer system, comprising the steps of receiving by a processor a request to read data from an uncached device, retrieving the data from multiple addresses located on the uncached device, combining the multiple addresses into one or more cache line formatted data blocks, and writing the one or more cache line data blocks to memory.
In yet a further embodiment, the invention comprises a system for achieving enhanced bandwidth utilization for an uncached device, comprising at least one processor, a memory, and an uncached device containing a plurality of addresses mapped as memory addresses. At least one processor is programmed to spread a cache line block of data into multiple lines of data useable by the uncached device, write the multiple lines of data to the uncached device, read multiple lines of data from the uncached device, and combine the multiple lines of data into a cache lin
Elmore Reba I.
Hogan & Hartson LLP
Kubida William J.
Meza Peter J.
SRC Computers, Inc.
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