Electrical computers and digital data processing systems: input/ – Input/output data processing – Data transfer specifying
Reexamination Certificate
2003-06-19
2009-10-13
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Input/output data processing
Data transfer specifying
C710S034000
Reexamination Certificate
active
07603491
ABSTRACT:
A command-response bus protocol reduces the number of response transactions generated on a bus. According to an embodiment, an array of data is divided into a number of packets and transmitted over the bus in respective transactions. The transactions each include a writeback flag, which is enabled for the last packet but otherwise disabled. When a receiver of the packets observes the enabled writeback flag, it generates a response transaction. The response transaction indicates either that all packets of the array were received properly or that the commanded operation has been completed for the entire array. Overall, the number of bus transactions are reduced with respect to alternative schemes that require a response transaction for each transmitted packet.
REFERENCES:
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patent: 6205498 (2001-03-01), Habusha et al.
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patent: 6788704 (2004-09-01), Lindsay
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patent: 2004/0034725 (2004-02-01), Elzur
Alireza Dabagh, Development Lead, Windows Networking, MicroSoft WinHEC 2002, NDIS 6.0, Apr. 16-18, 2002.
Dang Khanh
Intel Corporation
Kenyon & Kenyon LLP
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