Bandwidth-adaptive, hybrid, cache-coherence protocol

Details Bandwidth-adaptive, hybrid, cache-coherence protocol Bandwidth-adaptive, hybrid, cache-coherence protocol

2005-04-19

2005-04-19

Tran, Denise (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S146000, C711S207000, C709S224000, C709S230000

Reexamination Certificate

active

06883070

ABSTRACT:
A cache coordination mechanism for a multiprocessor, shared-memory computer switches between a snooping mechanism where an individual processor unit broadcasts or multicasts cache coherence messages to each other node on the system and a directory system where the individual processor unit transmits the cache control message to a directory which then identifies potential candidates to receive that message. The switching is according to the activity on the communication network used by the cache coherence messages. When network activity is high, a directory protocol is used to conserve bandwidth but when network activity is low, a snooping system is used to provide faster response.

REFERENCES:
patent: 6510496 (2003-01-01), Tarui et al.
patent: 6535957 (2003-03-01), Arimilli et al.
patent: 20010013089 (2001-08-01), Weber
Scott et al., “Performance of Pruning-Cache directories for large-Scale Multiprocessors” 1993, IEEE, vol. 4, No. 5, pp 520-534.*
Bilir, E. Ender et al., Multicast Snooping: A New Coherence Method Using a Multicast Address Network, ISCA'99 Submission, University of Wisconsin—Madison, pp. 1-22, May 2-4, 1999.

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