Band engineered nano-crystal non-volatile memory device...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S324000, C257S317000, C257SE29309, C365S185010, C365S185050

Reexamination Certificate

active

07851850

ABSTRACT:
Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal charge trapping in EEPROM and block erasable memory devices, such as Flash memory devices. Embodiments of the present invention allow a reverse mode gate-insulator stack memory cell that utilizes the control gate for programming and erasure through a band engineered crested tunnel barrier. Charge retention is enhanced by utilization of high work function nano-crystals in a non-conductive trapping layer and a high K dielectric charge blocking layer. The band-gap engineered gate-stack with symmetric or asymmetric crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.

REFERENCES:
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 5886368 (1999-03-01), Forbes et al.
patent: 6121654 (2000-09-01), Likharev
patent: 6514828 (2003-02-01), Ahn et al.
patent: 6586797 (2003-07-01), Forbes et al.
patent: 6642573 (2003-11-01), Halliyal et al.
patent: 6664589 (2003-12-01), Forbes et al.
patent: 6713810 (2004-03-01), Bhattacharyya
patent: 6743681 (2004-06-01), Bhattacharyya
patent: 6754108 (2004-06-01), Forbes
patent: 6759713 (2004-07-01), Bhattacharyya
patent: 6768156 (2004-07-01), Bhattacharyya
patent: 6778441 (2004-08-01), Forbes et al.
patent: 6784480 (2004-08-01), Bhattacharyya
patent: 6849464 (2005-02-01), Drewes
patent: 6864139 (2005-03-01), Forbes
patent: 6888200 (2005-05-01), Bhattacharyya
patent: 6900455 (2005-05-01), Drewes
patent: 6917078 (2005-07-01), Bhattacharyya
patent: 6933572 (2005-08-01), Bhattacharyya
patent: 7012297 (2006-03-01), Bhattacharyya
patent: 7042052 (2006-05-01), Bhattacharyya
patent: 2003/0042527 (2003-03-01), Forbes et al.
patent: 2003/0042532 (2003-03-01), Forbes
patent: 2003/0042534 (2003-03-01), Bhattacharyya
patent: 2003/0043632 (2003-03-01), Forbes
patent: 2003/0043633 (2003-03-01), Forbes et al.
patent: 2003/0043637 (2003-03-01), Forbes et al.
patent: 2003/0045082 (2003-03-01), Eldridge et al.
patent: 2003/0048666 (2003-03-01), Eldridge et al.
patent: 2003/0089942 (2003-05-01), Bhattacharyya
patent: 2003/0151948 (2003-08-01), Bhattacharyya
patent: 2003/0235064 (2003-12-01), Batra et al.
patent: 2005/0001232 (2005-01-01), Bhattacharyya
patent: 2006/0084214 (2006-04-01), Bhattacharyya
patent: 2006/0110870 (2006-05-01), Bhattacharyya
patent: 2006/0192240 (2006-08-01), Bhattacharyya
patent: 2006/0192243 (2006-08-01), Bhattacharyya
patent: 2006/0258090 (2006-11-01), Bhattacharyya et al.
patent: 2007/0045706 (2007-03-01), Bhattacharyya et al.
S. Okhomin, et al.; A Soi Capacitor-Less It DRAM Concept; IEEE International SOI Conference, Oct. 2001; pp. 153-154.
T. Ohsawa et al.; Memory Design Using One Transistor Gain Cell on SOI; IEEE International Solid State Circuit Conference; 2002; pp. 152-153 and p. 454.
P. Dimitrakis et al.; Silicon Nanocrystal Memory Devices Obtained by Ultra-Low-Energy Ion-Beam Synthesis; International Solid State Electronics, No. 48; 2004; pp. 1511-1517.
A. Bhattacharyya; Physical and Electrical Characteristics of LPCVD Silicon Rich Nitride; 1669thFall Meeting of the Electrochemical Society; 1984, p. 467c, 469c.
M. Koyanagi et al.; Metal Nano-Dot Memory for High-Density Non-Volatile Memory Application; IEEE SNVMW; 2004; 0-7803-8511-X/04.
M. Kanoun et al.; Electrical Study of Ge-Nanocrystal-Based Metal-Oxide-Semiconductor Structures forp-type Nonvolatile Memory Applications; Applied Physics Letters, vol. 84 No. 25; 2004; pp. 5079-5081.
C.M. Compagnoni et al.; Study of Data Retention for Nanocrystal Flash Memories; IEEE 41stAnnual Intl. Reliability Physics Symposium; 2003; pp. 506-512.
D. Zhao et al.; Simulation of Hetero-Nanocrystal Floating Gate Flash Memory; IEDM; 2004; pp. 1-3.
Y.Q. Wang et al.; Formation of Ge Nanocrystals in HfAIO high-kDielectric and Application in Memory Device; Applied Physics Letters; vol. 84 No. 26; 2004; pp. 5407-5409.
C.Gerardi et al.; Fast and Low Voltage Program / Erase in Nanocrystal Memories: Impact of Control Dielectric Optimization; Non Volatile Semiconductor Memory Workshop (NVSMW); 2004; p. 71.
B. Govoreanu et al.; a Figure of Merit for Flash Memory Multi-Layer Tunnel Dielectrics; Simulation of Semiconductor Processes and Devices; 2001; pp. 270-273.
C.M. Compagnoni et al.; Program/Erase Dynamics and Channel Conduction in Nanocrystal Memories; IEDM; 2003; pp. 22.4.1-22.4.4.
R. Ohba et al.; Impact of Stoichiometry Control in Double Junction Memory on Future Scaling; IEDM; 2004; pp. 36.7.1-36.7.4.
S. Lombardo et al.; Distribution of the Threshold Voltage Window in Nanocrystal Memories with Si Dots Formed by Chemical Vapor Deposition: Effect of Partial Self-Ordering; Non Volatile Semiconductor Memory Workshop (NVSMW); 2004; p. 69.
R. Gupta et al.; Formation of SiGe Nanocrystals in HfO2Using in situ Chemical Vapor Deposition for Memory Applications; Applied Physics Letters, vol. 84 No. 21; 2004; pp. 4331-4333.
S. Tiwari et al.; Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage; IEDM; 1995; pp. 20.4.1-20.4.4.
J.H. Chen et al.; Nonvolatile Flash Memory Device Using Ge Nano-Crystals Embedded in HfAIO High-k Dielectric; Non-Volatile Memory Workshop; 2005; p. 1124.
C. Lee et al.; Operational and Reliability Comparison of Discrete-Storage Nonvolatile Memories: Advantages of Single and Double-Layer Metal Nanocrystals; IEDM; 2003; pp. 22.6.1-22.6.4.
Y. Zhang et al.; Flash Memory Cell with LaAIO3(K=27.5) as Tunneling Dielectrics for Beyond Sub-50 nm Technology; Non-volatile Memory Workshop; 2004; pp. 1-2.
J.J. Lee et al.; Dielectric Engineering in Nanocrystal Memory Devices for Improved Programming Dynamics; IEEE 43rdAnnual Reliability Physics Symposium; 2005; pp. 668-669.
J.J. Lee et al.; Novel Nonvolatile Memory Device Using Metal Nanocrystals Embedded in High-K for Improved Data Retention; Nonvolatile Workshop; 2004; pp. 11.1-11.2.
B. Govoreanu et al.; Variot: A Novel Multilayer Tunnel Barrier Concept for Low-Voltage Nonvolatile Memory Devices; IEEE Electron Device Letters, vol. 24 No. 2; 2003; pp. 99-101.
K.K. Likharev; Riding the Crest of a New Wave in Memory; Circuits and Devices; Jul. 2000; pp. 16-21.
J. Willer et al.; 110nm NROM Technology for Code and Data Flash Products; Symposium on VLSI Technology Digest of Technical Papers; 2004; pp. 76-77.

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