Ballasting MOSFETs using staggered and segmented diffusion...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S355000, C257S357000, C361S056000

Reexamination Certificate

active

06927458

ABSTRACT:
An ESD protection circuit includes a field effect transistor device configured such that current flowing through a hot spot filament formed in a gate region must flow in a non-linear path from a drain contact to a source contact. Source diffusion areas are segmented and staggered relative to drain diffusion areas in order to provide the non-linear current path.

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K.G. Verhaege et al.; “Novel Design of Driver and ESD Transistors with Significantly Reduced Silicon Area”; 2001, pp. 1-12.
B. Keppens, et al.; “Area compact, ESD robust, Fully silicided NMOS using novel Active Area Ballasting (AAB) technique”; 2003, pp. 1-4.
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Karlheinz Bock, et al.; “Influence on Well Profile and Gate Length on the ESD Performance of a Fully Silicided 0.25 μm CMOS Technology”; Oct. 1998; pp. 286-294.
Tung-Yang Chen and Ming-Dou Ker, “Investigation of the Gate-Driven Effect and Substrate-Triggered Effect on ESD Robustness of CMOS Devices”; Dec. 2002; pp. 190-203.

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