Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-25
2004-05-25
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S356000
Reexamination Certificate
active
06740936
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits, in particular to electrostatic discharge (ESD) protection of the integrated circuit (IC).
BACKGROUND
ESD usually occurs during handling of IC devices, and consists of a very high positive or negative voltage being applied to an input/output pad of the IC device. The IC device must be protected from such events. In particular, the transistors of the IC, especially the thin gate oxides of the transistors, must be protected. As integrated circuit devices have become smaller, their tolerance of ESD events has become less. Thus, providing ESD protection has become more difficult. One kind of ESD protection device is a ballast resistor placed between a pad in the IC device and an input/output driver transistor that applies voltage to the pad or receives voltage from the pad. The fundamental problem with ballast resistors is that they consume significant silicon area. Since silicon area is the single most cost controlling element in IC production, there is a need to reduce silicon area.
FIG. 1
shows a side view cross section of a prior art transistor structure that includes a ballast resistor. A typical MOS transistor includes source region S, drain region D, separated by channel region C in the semiconductor substrate, over which is gate G. Source region S is contacted by contact N and drain region D is contacted by drain contact M. A lightly doped drain implant LDD is also applied to the source and drain regions to reduce current spiking at the junctions with the channel region. To form the ballast resistor
12
, drain region D is extended, and contact M is separated from drain region D. Contact N and a contact at gate G (not shown) lead to other structures internal to the IC device, and contact M leads to an input/output pad of the IC device.
As discussed by Ajith Amerasekera and Charvaka Duvvury in “ESD in Silicon Integrated Circuits”, © 1995 by John Wiley & Sons Ltd., at page 177, in a typical LDD structure, the LDD region is formed by phosphorus implantation with doses ranging from 10
13
/cm
2
to 10
14
/cm
2
. It is also possible to use arsenic as the implant species for the LDD. As shown in
FIG. 1
, the LDD implant
11
is selfaligned to the edge of polysilicon gate G, migrating slightly beneath the edge. The main source/drain (S/D) implant usually consists of arsenic with doses in the 2×10
15
/cm
2
to 5×10
15
/cm
2
range. In order to ensure that the LDD region
11
is not overdosed by the S/D implant, the S/D implant is self-aligned to a spacer
13
deposited against the gate.
As integrated circuit devices shrink (channel lengths decrease, source and drain regions decrease, gate oxides become thinner, wires become narrower), one area that can not become smaller is the ballast resistor. For a given semiconductor process technology, the ballast resistor must remain of a size that it can dissipate heat generated by high currents resulting from the high voltage ESD event without being damaged and thus the ballast resistor has a minimum width. But in order to have sufficient resistance to limit ESD current, the ballast resistor must have sufficient length. Thus the ballast resistor becomes a limitation to further shrinking of the IC device.
It would be desirable to keep the ballast resistor at the minimum width defined by the heat dissipation limit and at the same time meet resistance requirements. It would also be desirable to accomplish this reduction without adding complication to the existing manufacturing process technology.
SUMMARY OF THE INVENTION
According to the invention, the resistivity of the ballast resistor is increased by changing the shape of a mask in order to prevent some of the doping of the ballast resistor region. As discussed above, a drain region is typically doped twice, once for a drain diffusion and once for a lightly doped drain implant. According to the invention, a portion of one of these dopings is blocked by one or more mask strips extending across a line between the drain and the drain contact.
In one embodiment, strips are placed in the mask for forming the drain region. In another embodiment, strips are placed in the mask for forming the lightly doped drain. In either embodiment, there may be one or more strips.
The invention increases resistivity of the ballast resistor region and thus allows for reducing the length of the ballast resistor without introducing any additional process or masking steps. Thus the invention allows a reduction in IC die size without any loss in ESD immunity, or allows better ESD protection for a given die size.
REFERENCES:
patent: 4503448 (1985-03-01), Miyasaka
patent: 5477414 (1995-12-01), Li et al.
patent: 6054736 (2000-04-01), Shigehara et al.
patent: 6229183 (2001-05-01), Lee
“ESD In Silicon Integrated Circuits”, Design and Measurement in Electronic Engineering, 1995 by, John Wiley & Sons Ltd, pp. 176-186.
de Jong Jan L.
Gitlin Daniel
Jeong Jongheon
Karp James
Harms Jeanette S.
Munson Gene M.
Xilinx , Inc.
Young Edel M.
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